SU633016A1 - Arithmetic device - Google Patents

Description

The first outputs of which are connected to the control inputs of the shift registers, the first outputs of the first, second and third shift registers are connected respectively to the first inputs of the first, second and third adders, the outputs of which are connected to the first inputs of the respective shift registers, the second outputs of the second and the third shift registers are connected respectively with the first inputs of the fourth and fifth shift registers, the output of the fourth shift register is connected with the second inputs of the first and second adders The output of the fifth shift register is connected to the second input of the third subtractor, a calculation convergence analysis block is entered, the input of which is connected to the second output of the first shift register, the first and second outputs to the corresponding inputs of the control unit, and the third output to the control ones Adders Adders-Makers. In this case, the calculation convergence analysis block contains two comparison schemes, the outputs of which are connected respectively to the trigger inputs, which inputs are connected respectively to the first inputs of the And elements, the second inputs of which are connected to the clock bus, and the outputs of the And elements are connected respectively to the first and second outputs of the analysis block The inputs of the comparison circuit and the first input of the third element I are the inputs of the convergence analysis block, the second input of the third element I is connected to the clock bus, the output of the third element I through rety trigger to the third output calculating convergence analysis unit. Such a device extends the functionality and scope of the arguments. Fig. 1 shows a block diagram of an arithmetic unit; Fig. 2 shows a block diagram of the analysis of the convergence of the calculation. The arithmetic unit contains one-bit totalizers-subtractors 1-3, shift registers t-8, a calculation convergence analysis block 9 and a control block 10. The first outputs of shift registers 4-6 are connected respectively to the first inputs of adders-subtractors 1-, the outputs of which are connected respectively to the first inputs of these shift registers 4-6, the second outputs of which, respectively, are connected to the first converters of the analysis convergence analysis 9 , shift register 7 and engine register 8. The outputs of shift registers 7 and 8, respectively, are connected to the second inputs of adders-subtractors 1-2 and the second input of adder-subtractors 3, the first and second outputs of the convergence analysis block 9 are connected to the corresponding The control inputs 10 of the control unit, the third output with the control inputs of the totalizers subtractors 1-3, the outputs of the control unit 10 are connected to the control inputs of the shift registers 4th, the device inputs are the inputs of the shift register 4 for the value of the first argument X, shift register 6 for the value of the second argument Y and shift register 5 for the value of the third argument Z. The output of the device is the output of shift register 6, Block 9 of the analysis of the convergence of the calculation contains, for example, comparison circuits 11 and 12, triggers 1315, elements 16-18, and comparison circuit 11n is needed to compare the contents of shift register 4 with a logical zero, which is fed to one of the entrance. The other inputs are connected to the outputs of all bits, except for the sign one, shift registers 4, The sign bit is connected to one of the inputs of the second comparison circuit 12 and to the input of the And 18 element, The output of the comparison circuit 11 via the trigger 13 and the And 16 element is connected to the first output block 9, the output of the comparison circuit 12 through the trigger 14 and element 17 is connected to the second output of block 9, the second inputs of the elements 16-18 is connected to the clock bus 19, the output of the element 18 and 18 is connected to the trigger 15 whose output is connected 12 and the third output of block 9, Iteration nny calculation process based on the simultaneous addressing difference recurrence relations system, for example, for the binary notation system: 0.0 -2. , j2x „-O. , x .. Si.j, (, 1c X -, 0. 2о .. i + i ,, j Sij-2 -j2 VY.. -va Y. Y. NH,;) + - f, J ri, jl , i In.nZ

where i is the index number of iteration, j 0,1, ...

... CI is a measure of weight it | |

P is the number of bits.

The calculations in the arithmetic unit are carried out as follows.

Initially, shift value 4 is entered into the value of argument X, shift register 5 is set to the value of argument Z, and shift register 6 is set to value Y

In the initial iteration, clock pulses from the output of the control unit Yu start to flow only to shift registers 4 and 7, the content of which is summed algebraically in adder-subtractor 1. The result of the initial iteration is written into the higher bits of the shift registers 4. At the end of the initial iteration, The register contains the value X - Z.

At any l, jth iteration, from the outputs of control unit 10, sequences (series,) of clock pulses are output to shift the contents of the shift registers 7 and 8 by j bits to the right of the comma and advance the contents of the shift registers 4-S to the corresponding inputs of the adders "Count 1-3, The results of each iteration are recorded from the outputs of the adders-subtractors 1-3 by the lower bits forward and the higher bits of the shift registers 4-6, which are released when shifted, respectively, and move towards the lower bits to the beginning of these registers. each iteration of the signal from the clock bus 19 in the block

In analyzing the convergence of the calculations of gyu and the sign of the contents of the shift register 4, the next digit of the operator J, is formed; . way

install the trigger 15 in the appropriate position tiyrouiee. When the value is -; -1 torus subtracter 1 operates in close mode, adders-subtractors 2-3 in subtraction mode. When O, - + l, their twbo mode is reversed. At the iromene of the value of the next digit (- j to the comparison circuit 12, trigger 14 and submenus And 17 from the second output of block 9 to control block 10, a transition signal is output from j - magnitude to the next shift value by J 1 bits, t, e, A new iteration is increased by one. When the shift register 4 is zero from the output of the comparison circuit 11 through the trigger 13 and the element H 16 from the first output of block 9, a stop signal is output to the input of block 10, t, k, the calculation process is completed and the clock pulses on the next iteration, they are not issued. shift 6 is equal to the value of the quotient dividing the product of two arguments by the third.

The maximum calculation time in ticks is n (nnn) + fn where the number of additional bits to compensate for the error of truncation of numbers during the shift, and increases with decreasing argument Z, However, due to the asynchronous mode of operation for the majority of arguments, the calculation time was less than the maximum value that significantly less computation time using separate multiply and divide operations at comparable hardware costs.

The table shows an example of the calculation in an arithmetic unit for the values of the arguments X 0.5, Y 0.25 and Z 0.125.

For the current attribute values, the computation time is 2 (h + m) cycles or 30 cycles for 12-digit numbers.

Comparative tests of this arithmetic device with a known device have shown that this device has advanced functional capabilities that do not impose

There are no restrictions on the limits of variation of arguments and provides high speed at moderate hardware costs.

Claims (2)

Invention Formula An arithmetic unit containing a control unit, the outputs of which are connected to the higher inputs of the register The first slope of the first, second, and third shift registers are connected to the first inputs of the first, second, and third adders, the outputs of which are connected to the first inputs of the respective shift registers, the second outputs of the second and third shift registers are connected to the first moves of the fourth and fifth shift registers, the output of the fourth shift register is connected to the second inputs of the first and second adders-subtractors, the output of the fifth shift register is connected to the second input of the three This is the sum of the readers, which is designed to expand functionality by calculating the quotient of dividing the product of two arguments by the third argument and expanding the range of arguments, the device contains a calculation convergence analysis block whose input is connected to the second output of the first shift register. the first and second outputs - with the corresponding inputs of the control unit, the third output - to the control inputs of the totalizer DOB-subtractors. 2. The device according to claim 1, characterized in that the NTO unit of analysis of the convergence of the calculation contains two comparison circuits, the outputs of which are connected respectively to the inputs of flip-flops, the outputs of which are connected respectively to the first inputs of the And elements, the second inputs of which are connected to the clock bus, the outputs of the And elements are connected respectively to the first and second outputs of the analysis block, the inputs of the comparison circuits and the first input of the third element AND are the inputs of the convergence analysis block, the second input of the third element AND connected to the clock bus, the output of the third element and the third trigger to the third output of the unit of analysis of the convergence of the calculation.