SU717778A1 - Device for solving simultaneous differential equations - Google Patents

Description

(54) DEVICE FOR SOLVING OICTEM EQUATIONS OF DIFFERENTIAL,; , 3 717 riepBoiX) of the shift unit, the first, second and third outputs of which are connected to the second, third and fourth inputs of the first switch, the second, third and third outputs of which are connected to the fourth, fifth and sixth inputs of the recurrent computing unit, the second output is connected to the first input of the second 14) switch, the second input of which is connected to the input of the first sulshator and to the first output of the recurrent computation, the code of the first dryer is connected to the main input of the second shift unit and the second input of the second switch a, the first, second and third outputs of which are connected to the first, second and third inputs of the OR element, the output of which is connected to the input of the second adder. The output of which is connected to the input of the unit, the comparison, the output of which is connected to the input of the control unit, the fourth and outputs of the memory unit is connected to the second and third inputs of the second shift unit, the output of which is connected to the third input of the second I-torus switch, a fourth koibofiolxj is connected to the second output of the block of recurrent calculations, the fourth VS: rd of the second com- part; the mutator is connected to the second input of the first switch, the third input of which; The sixth output of the memory block is the inputs of the first and second block of shifts, the memory block, the block of reckreatic calculations, the first and second switches and the second and second switches, which were compared with the corresponding outputs of the control block. In addition, a computational block contains blocks (multiplication, adder, inverter, and OR elements, the output of the first of which is connected to the first input of the first multiplication unit, the second (INPUT of the first block of recurrent calculations, the output of the multiplication unit is connected to the first input) cerned OR f, which VgHOD OLE DyyoY with hDom suSha ora whose output podklShoy iSejpfiowy to the input of the second e "(ShUKye Nij,: YSHSCH wherein a first output of rekkurentnyh computing and coupled to the input of inverter pa, whose output is yzyl the second output of the recurrent calculations block, the second inputs of the second OR element and the second multiplication block are the second and third blocks of the recurrent computation block, the first, second and third inputs of the first, respectively. 4 LI are the fourth, fifth and sixth inputs of the block recursive computing, the control input of the summer is the control input of the recurrent computing unit. The drawing shows the proposed device. The device contains the information shift block 1, the switch block 2, the rekkur block 3 power calculations, memory block 4, control block 5, adder 6, switch block 7, element OR 8, adder 9, block 10 of the comparison, block 11 offset g. The information shift block 1 consists of the elements OR 32, which store the solutions 12, 23, and 33. The switch block 2 consists of AND 13-16 elements. Block 3 of recurrent calculations consists of the elements of OR 17, the first block of 18 multipliers, the elements of OR 19, and the block 2O of accumulating adders; block mark. The shift unit 11 consists of memory registers 24 and 25 and a block 26 of in-i sign vertexes. Switch block 7 consists of control trigger 27 and switches 28-31. The work of the proposed innumeral system is carried out on the example of solving systems of differential equations of the form where g is the 1st time L (r; is the matrix of variable coefficients; i (-t) is the vector of right parts; t is the time; (0) - the initial value of X (t). Using the Taylor T-transformation, this system is reduced to the form;.), A, (e) X. . (K), x., ((4H), where X. (K) is a 1c -l discrete vector representing the vector Th (t) vector functions; F, (H) X-X discrete vector representing the vector fi (t) vector functions; A (e) .. matrix —x sampling, representing the matrix Av (t) of the matrix function. The operation of the number system starts from the output of control signals from the outputs of control unit 5 to the control inputs of memory block 4 and register 24 and 25 When these signals arrive, the readout from the memory block 4 and the initial conditions are stored in the memory registers 24 and 25. The register value 24 is entered into register 24 Scratch OS-Simultaneously from the memory block 4, the third inputs of the information shift block 1; the vector comes in. According to the control signals from block 5 arriving at the corresponding control inputs, zero initial conditions are set in the memory registers 33, 23 and 12 , to adders 20, 6, 9, comparison block 10 and control for the trigger trigger 27. According to the control signals from block 5, the incoming inputs to the switch 31 of the switch block 7 are inverted vector discrete (- (0)) from the outputs of block 26 si markers through the switch 31 enters to the third inputs of the elements OR 8, and from the outputs of the latter to the input of the adder 9. According to the control signals received from the control unit 5 to the control inputs of the adder 9, the zero code and the value of the vector vector entered into it (X- ( (o)} When the control signals from block 5 are received sequentially, the control inputs of the storage registers 12, 23 and 33 are shifted to information in block 1. In retarters 12 there are recordings from the information stored in register 23 and the last information stored with in register 33. In this case, register 33 records information arriving at the input of information shift unit 1, i.e. in the first step, the value of HoSo vector). After that, the control signals from block S are set to zero of the adder 6. With the flow of signals from control block 5 to the control. the inputs of switch 14 and switch 2, the value of the discrete vector stored in the memory register 33, goes through the opening element AND 14 to the first inputs of the elements OR 17 of the block 3 of recurrent allocations and from the outputs of block 17 to the first inputs of the block 18 of multipliers. After that, according to control titles, coming from control block 5 to the control inputs of memory block 4, reading from block 4 to the second inputs of the OR elements 19 is carried out sampling vector values Fi (X) According to the control signals from block 5, pos; the control inputs of block 20 accumulating adders, is the summation of the vector Fi () arriving at the inputs of block 2 from the outputs of the OR 19 elements, with the value found in block 20 (in the first scale of the WTO system, the code is zero). After that, the control signals from block 5 read from the memory block 4 to the second inputs of the magnitude multiplier 18 block. (Ai (0)) the value of the product (- A (O) Xi (O)) comes from the outputs of block 18 through block 19 to the input of block 20 of adders, where it is summed up in the next system cycle (when control signals are received at block 5) (in the next cycle from memory block 4 to the second inputs of the second block 21 multipliers, calculate the corresponding value of the coefficient H / (Kt- | - at the outputs of block 21 the value of the discrete vector X -} () / isO is formed, and the outputs of the block 22 of the sign inverters are its inverse sign In the next cycle, the received vector diokret enters the adder 6 and through the open single signal from the inverse output of the control trigger 27 element AND 28 of the switch 7 to the first inputs of the elements OR 8. In the adders 6 and 9, the control signals from block 5 determine expressions Xn (0) X | (i). and the left part of the inequality, 11 (21) X. (K) -X., (0) 6 corresponding to 0 BUT. In the next cycle, it is checked in block 1O of the comparison conditions of inequality. If it is executed and re-covered the entire integration interval, then the calculations are stopped. If the ending condition is not fulfilled, then from control block 5 control sequences are sequentially fed to memory registers 25 and 24 of the shift block; 11, the value of discrete Ho (0) written in register 24 is shifted to register 25, and the value of new the discrete vector (O) from the output of the adder 6 is recorded in the register 24, the next clock cycle is supplied with control signals to the FROM element 7, and the new value of the XiviCO discrete vector) through the open element I 30 is fed to the first inputs of the first 1 scoring information instead of vector fo (O) received from memory block 4. After that, the regasters 33, 23, and 12 of adders 20, 6, and 9 of the comparator block 10 and the control trigger (return to label No. 1) are set to zero, similar to the description above, and the follow-up is performed, the calculation step is: / shy kret X ;. (1s). If the conditional termination is not fulfilled, then the control unit trigger 27 is installed on the opposite side of the block of 20 nakagahvakashchy adders and iamen of the control trigger 27 on the opposite - the second element 29 opens it from its direct output and the zero element of the reverse output leaves the first element element 28 of the switch 7 in the next cycle of calculations, the input of the adder 9 receives the inverse value of the vector discrete from the outputs of the block 22 of inverters. By signaling the signal from block 5, element I 13 of switch 2 opens and the value of the discrete vector from the second steps of block 3 of the calculation calculations through the open element And 13 enters the second inputs of block 1 of information shift. After this, a return is made to label No. 2 of the algorithm of operation of the sys- tems; in the register 23 of block 1, it writes the value of the vector discrete (Co (0) j to register 33 — the value of the vector discrete ° C) and, similarly, the vector Tcret Ho (2). The described device, due to the presence of new elements and the connections between them, allows to increase the accuracy of solving systems of differential equations. The formula for a tob is in 1. Device for solving systems of differential equations, containing a control block, a memory block, iotepB, and a second switchboard, 6 tons of which, in order to increase accuracy devices, the first and second blocks of shift, the block of recursive calculations, the first and second adders, the OR elements and the comparison block, in addition, the first, second and third outputs of the memory block, are connected to the first, second and third inputs block rekkursentvyh calculations first of which is connected with the first input of the first switch, the first you of which is connected to the first one of the first shift, the first, second and third outputs of which are connected to the second 1RYM, TtpeTbBM and the fourth inputs of the second switch, the second, third and fourth outputs of which are connected to the fourth , the fifth and sixth inputs of the recurrent computing unit, the second output of which is connected to the first input of the second switch, the second input of which is connected to the input of the first adder and to the first, output of the recurrent calculator., the output of the first adder, soy inn with the first input of the second shift unit and with the second input of the BTqporo switch, the first, second and third outputs of which are connected to the first, second and third inputs of the OR element, the output of which is connected to the input of the second adder, the output of which is connected to the input of the comparison unit, the output of which is connected to the input of the control unit, the fourth and fifth outputs of the memory unit are connected respectively to the second and third inputs of the second shift block, the output of which is connected to the third input of the second switch, the fourth input of which is connected The second output of the second switch is connected to the second input of the first switch, the third input of the kitbra is connected to the sixth memory module, the control inputs of the first and second byoko shifts, the memory block, the recurrent computing unit, the first and the second adder, the first and second switch, the comparison unit is connected to the corresponding outputs of the control unit, 2. The device according to claim 1, characterized in that the recursive computing unit contains multiplication units. the adder, the inverter and the OR elements, the output of the first of which is connected to the first input of the first multiplication unit, the second input of which is the first input b; reclocking the calculations, the output of the multiplication unit is connected to the first input of the second OR element, the output of which is connected to the input of the adder, the output of which is connected to the first input ™, the second multiplication unit, the output of which is the first output of the recurrent computing unit and connected to the input of the inverter, the output of which is the second output of the recurrent computing unit eny, second inputs of second OR and the second multiplication unit are respectively second and third inputs rekkurenttilh computing unit, the first, second and third inputs of first OR are respectively chet9 71777810

twist, fifth and sixth inputs of block-1. USSR author's certificate

recursive computing, control number 481041, cl. Q 06 Q 7/34,

the input of the adder is the manager 15.08.75.

input block recurrent computing. USSR author's certificate

Sources of information, 5 No. 463980, CP. G- 06T 1/02,

The results are taken into account during the examination 05.05.75 (prototype).

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Claims (2)

1. A device for solving systems of differential ⁴⁰ differential equations, comprising a control unit, a memory unit, first and second switches, distinguished by the fact that, in order to improve the accuracy of the device, ⁴⁵ first and second shift blocks, a block are additionally introduced into it rivers — competitive calculations, the first and second adders, OR elements, and a comparison unit, the first, second, and third outputs of the memory unit being connected respectively to the first, second, and third inputs of the recursive computing unit, the first output of which is connected to the first Input of the first of the first switch, the first * output of which is connected to the first input of the first shift unit, the first, second, and third outputs of which are connected to the second, third, and fourth inputs of the first switch, the second, third, and fourth outputs of which are connected to the fourth, fifth, and sixth inputs recursive computing unit, the second output of which is connected to the first input of the second switch, the second input of which is connected to the input of the first adder and to the first, the output of the recursive computing unit, the output of the first adder, is connected to the first input the house of the second shift unit 'and with the second input of the second switch, the first, second and third outputs of which are connected to the first, second and third inputs of the OR element, the output of which is connected to the input of the second adder, the output of which is connected to the input of the comparison unit, the output of which is connected to the input of the control unit, the fourth and fifth outputs of the memory unit are connected respectively to the second and third inputs of the second shift unit, the output of which is connected to the third input of the second switch, the fourth input of which is connected to the second ode to the recursive computing unit, the fourth output of the second switch is connected to the second input of the first switch, the third input of which is connected to the sixth output of the memory unit, the control inputs of the first and second shift units, the memory unit, the recursive computing unit, the first and second adder, the first and second switch , comparison unit connected to the corresponding outputs of the control unit. 2. The device according to π. 1, characterized in that the recursive computing unit contains multiplication units, an adder, an inverter and OR elements, the output of the first of which is connected to the first input of the first multiplication unit, the second input of which is the first input of the recursive computing unit, the output of the multiplication unit is connected to the first the input of the second OR element, the output of which is connected to the input of the adder, the output of which is connected to the first input— to the second multiplication block, the output of which is the first output of the recursive computation block and connected to the input of inv A vector whose output is the second output of the recursive computation block, the second inputs of the second OR element and the second block are multiplication- | With the second and third inputs of the recursive computation block, respectively, the first, second, and third inputs of the first OR element are the fourth, fifth, and sixth inputs of the recursive computation block, the control input of the adder is the control input of the recursive computation block.