RU1781684C - Device for computation of discrete fourier transform - Google Patents

Abstract

The invention relates to computing, is intended to calculate two-dimensional discrete Fourier transform and digital filtering, can be used in digital signal processing systems. The purpose of the invention is to expand the functionality of the device. This goal is achieved due to the fact that the device contains an information input, information output, two inputs for setting the operating mode of the device, a control unit, a memory block of rotary factors, N computational cells (NxN is the dimension of the two-dimensional discrete Fourier transform), each of which contains 2 multipliers, 2 adders, switch, inverter, ROM, I element, 3 triggers, 4 registers, 2 N buffer registers. 3 ill.

Description

FIELD: computer engineering. SUBSTANCE: invention is intended for calculating a single and two-dimensional discrete Fourier transform and digital filtering procedure. The invention can be used in digital signal processing systems.

An object of the invention is to expand the functionality of a device.

In FIG. 1, 2 are structural diagrams of a device and a computational cell; in FIG. Figure 3 shows an example of a functional block diagram of a control unit.

The device (Fig, 1) contains information input 1, block 2 ROM, blocks 3.1. ... 3.N computational cells, control unit 4, clock generator 5, inputs 13, 14 for setting operating modes.

Computational cell VYA (Fig. 2) contains an input data register 23.1, a trigger 24.1 to enable input data writing, an inverter 38.1, an And 39.1 element, a register of rotary factors storage 25.1, a multiplier 26.1, a trigger 27.1, an adder 28.1, buffer registers 29.1.1

29.1.N, switch 30.1, buffer registers

31.1.1 31.1.N, trigger trigger 32.1

by the switch, register 33.1 of the address of the rotary factor, 34.1 - ROM of the rotary factors, multiplier 35..1, adder 36.1, register 37.1.

The output of trigger 24.1 is fed to the input of AND 39.1, the second input of which receives inverted clock pulses from the output of the inverter 38.1. The output of AND 39.1 is fed to the sync input of the data register 23.1 and to the output 17.1 of the EW. The output 17.1 VL is connected to the input 7.1 + 1 + 1-nd VL.

Inverted clock pulses are fed to the sync inputs of triggers 27.1,

H 00

about

00

32.1, registers 25.1,29.1.129.1.N, 31.1.1,

..., 31.1.N, 33.1. 37.1.

When applying to input 22 of register 25.1 logical 1, information is written to the register in each clock cycle, when applying to input 22 log. About register goes into storage mode.

The output of the register 25.1 is connected to one of the inputs of the multiplier 26.1, the second input of which is connected to the output of the register 23.1. The output of the register 25.1 is connected to the output of the VL 16.1, which is connected to the input 6.1 + 1 of the next VL.

The output of flip-flop 27.1 goes to the output of 18.1 V I, which is connected to the input 8.1 + 1 of the next VV, and also to the control input of the operation code of the adder 28.1. One of the inputs of the adder is connected to the output of the multiplier 26.1. The second input of the adder 28.1 is connected to the output of the buffer register 29.1.N. The output of the adder 28.1 goes to the input of the buffer register 29.1.1, as well as to one of the inputs of the switch 30L. The output of flip-flop 32.1 is connected to the control address of the switch 30.1, as well as to the output 19.1 of the CW, which is connected to the input 9.1 + 1 of the next CW.

The output of the switch 30.1 is connected to the input of the buffer register 31.1.1, as well as to the first input of the multiplier 35.1. The output of the buffer register 31.1.N is connected to the second input of the switch 30.1.

The output of the register 33.1 is connected to the address input of the ROM 34.1, as well as to the output of the 23.1 VV, which is connected to the input 10.1 + 1 of the next VV. The output of the ROM 34.1 is fed to the second input of the multiplier 35.1.

Input 11.1 receives a logic level 0, which is fed to one of the inputs of the adder 36.1, the second input of the adder 26.1 is connected to the output of the multiplier 35.1. The output of the adder 36.1 is connected to the input of the register 37.1, the output of which 21.1 is connected to the input 11.2 of the next VL.

The control unit (Fig. 3) for N 3 contains a clock input 12, operation mode inputs 13.14, 3 CT1, CT2, STZ dividers, DC1, DC2 decoders, MS switch, trigger T, two inverters, two elements EXCLUSIVE OR, OR element.

The STZ counter is connected in series to the ST2 counter and makes a count through 3 clock pulses, the outputs of the ST1 counter are connected to the ROM block 2, the high-order bit of the ST1 counter is fed through the inverter to the trigger input T, the input of which is connected to level 0, the output of trigger 22 is connected to 25.1 VJ.- register register control inputs. - -

We assume that the convolution calculation mode is established after calculating the DFT, i.e., to the beginning of the convolution calculation, trigger 1 is written as logical 1. Then, after 3

the trigger clock will be reset and prohibit writing to registers 25.1 VY.

The outputs of the CT2 counter are connected to the address inputs of the DC1 decoder and arrive at the MS switch, the last time

0 of the CT2 counter is fed to the synchro input of the STZ counter and provides its count after 3 clock cycles. The outputs of the STZ counter are connected to the address inputs of the DC2- decoder and are sent to the MS switch. The output of the switch 5 is fed to the information input of register 33.1 of the VL, the output of which is connected to the information input of register 33.2 of the next VL, as well as to the ROM of the turning factors 34.1. Output 7.1 connected

0 to the D input of trigger 24.1, provides the necessary write mode to registers 23.1. The output 9.1 is connected to the input of the trigger 32.1, the output of which is connected to the address input of the switch 30.1 and to the D input of the trigger

5 32.2 of the next EW. By output 9.1, switches 30.1 are switched according to the mode of operation.

Output 8.1 is connected to the D input of trigger 27.1, which provides the required operating mode of adders 28.1 (A + B or A + 0). In the mode of one-dimensional DFT, logic 1 is supplied to input 13 and logical 0 to input 14. In this case, the counter CT1 is in the zero state, the trigger T at the input S

5 is set to logical 1, the output of the OR element is logical 1, which is fed to the address input of the switch MS, which switches the outputs of counter CT2 to output 10.1. Log 1 output

0 of the OR element goes to output 8. by setting the operating modes of the adders 28.1-A + O, it also goes to the input W of the DC2 decoder, providing a log for all its outputs. 1. At the output, EXCLUSIVE OR 9.1 - log. 0.

5 Before the beginning of the 1st measure, the output 7.1 will be a log. 1, on the first and second measure-log. Oh, the next clock will reset the counter and output 7.1 will again log. 1. Thus, in this mode of operation, output 7.1

0 sequence 100100 will be formed ....

In convolution mode, a log is sent to input 13. Oh, input 14 is a log. 1. At the same time, the counter CT2 is in the reset state, on

5 output 10.1 - zero address. Similar to the mode of one-dimensional DFT at the output 9.1 - log. Oh, output 8.1 -log. 1. At all outputs of the DC1 decoder - log. 1, output 7.1 - log. 1, the addresses of the ROM block 2 are set at the outputs of the counter CT1. After 3 first

The clock trigger T is reset, thereby writing to the registers 25.1 of all EWs is reversed.

In 2D DFT mode, a log is sent to inputs 13, 14. 0. In this case, all three counters ST1, ST2, STZ work. At output 22, a log is constantly present. 1. At the exit 8.1 - a log. O (mode A + B totalizers). Similarly to the one-dimensional DFT mode, a sequence 100100 ... is generated at the output 7.1. At the output 9.1, a sequence 111111000111111000 ... is formed, which is fed to the input of the trigger 32.1, the output of which controls the switching of the switch 30.1.

The operation of the device in calculating the one-dimensional DFT.

The device evaluates the following expression:

Foo

2A (N)

k

W, k 0, N-1

A (N) - element of the initial action of the vector

AND . . Dimensions N i

F (k) - elements of the output vector of the coefficient in Fourier Dimensions N W - weighting factors M - number of the processed array.

As an example, let us consider the operation of the device when calculating the DFT algorithm for N 3. When calculating a one-dimensional DFT, the log level is applied to input 13. 1, input 14 - log. 0. At the same time, the address 0 is set on block 2 of the ROM, and at the output of block 2W 1, a 6.1 log signal appears at the input. Oh, at input 14 of the mouth, the trigger T is pushed into the log state. 1, which is fed to input 22 of all EWs. Input 7.1 receives the sequence 100100100 .... Input 9.1 receives the level log. Oh, input 8.1 - log. 1, input 11.1-log. 0. Inputs 10.1 receive addresses from the CT2 counter at each clock cycle of the device.

1st beat.

On the edge of the 1st clock pulse, a log is recorded in trigger 24.1. 1, the occurrence of which at the trigger output allows the recording of the first element A (0) in register 23.1, log. 1 at input 22 allows the entry in register 25.1 of the value W (0) 1, Log. 1 at input 8.1 is recorded in flip-flop 27.1 and sets on the control input of adder 28.1 the pass-through mode of the operand (A + 0). At the output of the multiplier 26.1 is formed. A (0) W (0) A (0), at the output of the adder 28.1 - A (0), the value of which through the switch 30.1 is fed to the input of the multiplier 35.1. The value of the ROM address is written to

register 33.1 and the value W (0) appears at the second input of multiplier 35.1. In the multiplier 35.1, A (0) W (0) is executed, the multiplication result is fed to the input of the register

5 amounts 37.1. 2nd beat.

On the D-input of the trigger 24.1 receives a log. Oh, on trigger 24.2 - log. 1, on trigger 24.3 - log. 0. The appearance of the log. 1 at the trigger output

0 24.2 allows the value of A (1) to be written to register 23.2, A (0) W (0) is written to register 37.1, and A (0) is written to register 23.1. Similarly to the 1st step, the value A (1) appears at the input of the multiplier 35I2, at the second

At the input of which W (0), the value A (1) W (0) appears at the input of adder 36.2, at the input of register 37.2 the value A (0) W (0) + A (1) W (0) appears at the input of the register

37.1-A (0) W (0). 0 3rd beat.

On the D-input of the trigger 24.1 receives a log. Oh, on trigger 24.2 - log. Oh, on trigger 24.3 - log. 1, according to venylogue. 1 at the output of trigger 24.3 allows writing the value of A (2) to register 23.3,

5, A (0) W (0) is written in register 37.1, in the 37.2 register the value A (0) L / (0) + A (1) W (0) is analogous to the 2nd measure, the value A (2) appears on the input of the multiplier 35.3, at the second input of which W (0), the value A (2) W (0) appears at

0 adder 36.3 input, register output

37.2 the value A (0) W (0) + A (1) W (0) appears, at the input of the register 37.3 - A (0) W (0) + A (1) W (0) + + A (2 ) W (0), at the input of the register 37.2 - A (0) W (0) + A (1) W (0).

5 4th beat (similar to 1st beat).

On the D-input of the trigger 24.1 receives a log. 1, to trigger 24.2 - log. Oh, on trigger 24.3 - log. 0. The appearance of the log. 1 at the output of trigger 24.1 allows writing the value of A (0) to the register

0 23.1, A (0) W (0) is written in register 37.1, in the 37.2 register the value A (0) W (0) + A (1) W (1) is analogous to the 1st measure, the value A (0) after is at the input of the multiplier 35.1, at the second input of which W (0), at the output of the adder

5 36.1 - A (0) W (0). At the output of the multiplier 35.2 - A (1), at the second input of which (2) at the input of the register 37.2 - A (0) W (0) + A (1) W (2), at the input of the multiplier 35.3 - A (2), at the second input of which W (2), at the input of the register 37.3 0 A (0) W (0) + .A (1) W (1) + A (2) W (2) at the output of the device, the value 1- th Fourier coefficient:

F (0) - A (0) W (0) + A (1) W (0) + A (2) W (0).

5th beat (similar to 2nd beat).

On the D-input of the trigger 24.1 receives a log. Oh, on trigger 24.2 - log. 1, to trigger 34.3 - log. Oh, there is a log. 1 at the output of trigger 24.2 allows writing the value of A (1) to the register

23.2, A (0) W (0) is written in register 37.1, in

register 37.2 - value A (0) W (0) + A (1) W (2)

at the input of the multiplier 35.2 - A (1), at the second

whose input (0),

at the input of the register 37.2 - A (0) W (0) + A (1) W (0) 5

at the input of the multiplier 35 3 - A (2), at the second

which input (41,

at the input of the register 37.1 - A (0) W (0)

at the input of the register 37.3 - A (0) W (0) + A (1) W (2) +

+ A (2) W (4) 10

the value appears at the output of the device

2nd Fourier coefficient:

F (1) A (0) W (0) + A (1) W (1) + A (2) W (2)

6th beat (same as 3rd beat)

On the D-input of the trigger 24.1 receives a log.

Oh, on trigger 24.2 - log. ABOUT,

on trigger 24.3 - log. 1, the appearance of the log. 1 on

trigger output 24.3.20

Allows writing the value of A (2) to the register

23.3

at the input of the multiplier 35.3 - A (2). on the second

whose input is W (0),

at the output of the multiplier 35.3 - A (2) W (0) 25

the value appears at the output of the device

3rd Fourier coefficient:

F (2) - A (0) W (0) + A (1) W (2) + A (2) W (4)

Further operation of the device is similar to the algorithm described above.

When implementing discrete convolution, the device calculates the output samples in accordance with the expression:

X (k) SA (k-N) H (N)

k

A (k-N) - elements of the input array,

H (N) - impulse response coefficients.

A log, 0, is fed to the input 13 of the control unit, and a 14-log to the input 14. 1. At the output of the CT2 counter, a zero address is permanently set, which is fed to the input 10.1 of the VL, ensuring the installation of one of the factors on the multipliers x 35.1 equal to one.

The control unit is considered for a case of impulse response of length equal to 3.

Calculation of the discrete convolution after calculating the DFT, i.e., we consider that at the output of the control unit 22 the level is log. 1. At the output 7.1 - a constant level log. 1, which provides the entry of input data into registers 23.1 at each clock cycle; at output 9.1, a log. Oh, output 8.1 - log. 1.

During the first three clock cycles, the coefficients are loaded into registers 25.1,25.2, 25.3. At the 4th bar, the trigger T is reset to zero

inputs 22 of all VL the log goes. Oh, which prohibits the recording of information in the registers 25.1,25.2,25.3.

The operation of the device in the calculation of two-dimensional DFT.

In 2D DFT mode, the device calculates the following expression:

F (N) - x (X x),

where X is the matrix of input samples of dimension

, - matrices of weight coefficients of dimension.

Consider the operation of the device on the example of N 3

GC (11) X (12) X (13)

X (21) X (22) X (23)

X (31) X (32) X (33)

(11) (12) (13)

(21) (22) (23)

(31) (32) (33)

(11) (12) (13)

(21) (22) (23)

(31) (32) (33)

0

5

0

5

0

5

Logon levels are supplied to inputs 13. 14 of the control unit. O, at input 14 it sets the trigger T to the log state. 1, which is present at the inputs of 22 VL, permits writing to registers, 25.1 W values, Counter st. 1 provides a change of address of the block 2 ROM at each clock cycle. Block 2 stores the values of W.

The counters ct 2, ct 3 provide a change in the addresses of the ROM WL, where W values are stored every 3 clock cycles.

The input 7.1 from the control unit receives the sequence 1001001 ... (as in the one-dimensional DFT mode). managing writing data to registers 23.1.

Input 9.1 receives the sequence 111111000111111000 ..., which controls the switching of switches 30.1.

Input 8.1 receives the log level. 0. which switches the adders 38.1 to the mode of calculating the sum of two operands (A + B).

The input 10.1 receives the address value; W every 3 cycles. We consider that in registers 29.1, 31.1 zeros are written before the calculations.

1st beat.

A log is written to the trigger 24.1 along the edge of the first clock. 1 from input 7.1, which allows the passage of an inverted clock pulse through element 39.1. The value of X (11) is written to

register 23.1, and the value (11) is written to register 25.1,

at the output of the multiplier 26.1- X (11) W (11)

at the output of the adder 28.1 - X (11) W (11)

2nd beat.

A trigger is written to trigger 24.2. 1, and a log is written to triggers 24.1. 1, and in triggers 24.1. 24.3 - log. 0.

The value X (12) is recorded in register 23.2,

in the register 25.1 is written the value of W (21)

in register 25.2 - the value of W (11) at the output of the multiplier 26.1 - X (11) W (21) at the output of the multiplier 26.2 - X (12) W (11) in the register 29.1.1 - the value of X (11) W (11) at the output of the adder 28.1 - the value of X (11) W (21)

at the output of the adder 28.2 - the value of X (12) W (11)

3rd beat.

In trigger 24.3, 1 is written, and in triggers 24.1, 24.2 it is written 0.

The value of X (13) is written to register 23.3, the value of W (31) is written to register 25.1; the value of W (21) is written to register 25.2; the value of W (11) is written to register 25.3 at the output of the multiplier 26.1 - X (11) W (31) at the output of the multiplier 26.2 - X (12) W (21) at the output of the multiplier 26.3 - X (13) W (11) at the output of the adder 28.1 - X (11) W (31) at the output of the adder 28.2 - X (12) W ( 21) at the output of the adder 28.3 - X (13)) at the output of the register 29.1.1 -X (11) W (21) at the output of the register 29.1.2 - X (11) W (1)

at the output of the register 29.2.1 - X (12) W (11)

4th beat.

In trigger 24.3, 0 is written, in trigger 24.1 - 1, in trigger 24.2 - 0. The value X (21) is written to register 23.1, the value W (12) is written to register 25.1; the value W (31) is written to register 25.2; the value of W (21) at the output of the multiplier 26.1 - X (21) W (12) at the output of the multiplier 26.2 - X (12) W (31) at the output of the multiplier 26 3 - X (13) W (21) at the output of the adder 28.1 - X (21) W (12) + + X (11) W (11)

at the output of the adder 28.2 - X (12) W (31) at the output of the adder 28.3 - X (13) W (21)

at the output of the register 29.1.1 - X (11) W (31) at the output of the register 29.1.2 - X (11) W (21) at the output of the register 29.1.3-X (11) W (11) at the output of the register 29.2. 1 - X (12) W (2l) at the output of the register 29.2 2 - X (12) W (11)

at the output of the register 29.3.1 - X (13) W (11)

5th beat.

0 is written to trigger 24.3, 24.1-0 to trigger, 24.2-1 to trigger. the value of X (22) is recorded in register 23.2,

in the register 25.1 is written the value of W (22)

in register 25.2 is written the value of W (12)

in the register 25.3 is written the value of W (31)

at the output of the multiplier 26.1 - X (21) W (22)

at the output of the multiplier 26.2 - X (22) W (12)

at the output of the multiplier 26.3 - X (13) W (31)

at the output of the adder 28.1 - X (21) W (22) +

+ X (11) W (21)

at the output of the adder 28.2 - X (22) W (12) +

+ X (12) W (11)

at the output of the adder 28.3 - X (13) W (31)

at the output of the register 29.1.1 - X (21) W (12) +

+ X (11) W (11)

at the output of the register 29.1.2 - X (11) W (31)

at the output of the register 29.1.3 - X (11) W (21)

at the output of the register 29.2.1 - X (12) W (31)

at the output of the register 29.2.2 - X (12) W (21)

at the output of the register 29.2.3 - X (12} W (11)

at the output of the register 29.3.1 - X (13) W (21)

at the output of the register 29.3.2 - X (13) W (11)

bth beat.

In trigger 24.3, 1 is written, in trigger 24.1 - 0, in trigger 24.2 - 0. The value X (23) is recorded in register 23.3, the value W (32) is written in register 25.1; the value W (22) is written in register 25.2; in the register 25.3 it is written the value of W (12) at the output of the multiplier 26.1 - X (21) W (32) at the output of the multiplier 26.2 - X (22) W (12) at the output of the multiplier 26.3 - X (23) W (12) at the output of the adder 28.1 - X (11) W (31) «+ X (21) W (32)

at the output of the adder 28.2 - X (12) W (11) + + X (22) W (22)

at the output of the adder 28.3 - X (13) W (11) + + X (23) W (12)

at the output of the register 29.1.1 - X (11) W (21) + + X (21) W (22)

at the output of the register 29.1.2 - X (11) W (11) + + X (21) W (12)

at the output of the register 29.1.3 -X (11) W (31) at the output of the register 29.2.1 - X (12) W (11) + + X (22) W (12)

at the output of register 29.2.2 -X (12) W (31) at the output of register 29.2.3 -X (12) W (21) at the output of register 29.3.1 - X (13) W (31) at the output of register 29.3. 2 -X (13) W (21) at the output of the register 29.3.3 - X (13) W (11)

7th beat.

In trigger 24.3, 0 is written, in trigger 24.1 - 1, in trigger 24.2 - 0. The value X (31) is written in register 23.1, at the input 9.1 of trigger 32.1 a log appears. 0. The inverted clock sets the trigger to 0 and the switch 30.1 switches the output of the adder 28.1 to the input of the multiplier 35.1 and to the output of the buffer register 31.1.1.

In register 25.1 is written the value of W (13)

in the register 25.2 is written the value of W (32)

in the register 25.3 is written the value of W (22)

at the output of the multiplier 26.1 - X (31) W (13)

at the output of the multiplier 26.2 - X (22) W (32)

at the output of the multiplier 26.3 - X (23) W (22)

at the output of the adder 28.1 - X (11) W (11) +

+ X (21) W (12) + X (31) W (13) - C (11)

at the output of the adder 28.2 - X (12) W (3T) +

+ X (22) W (32)

at the output of the adder 28.3 - X (13) W (21) +

+ X (23) W (22)

at the output of the register 29.1.1 - X (11) W (31) +

+ X (21) W (32)

at the output of the register 29.1.2 - X (11) W (21) +

+ X (21) W (22)

at the output of the register 29.1.3 - X (11) W (11) +

+ X (21) W (12)

at the output of the register 29.2.1 - X (12) W (21) +

+ X (22) W (22)

at the output of the register 29.2.2 - X (12) W (11) +

+ X (22) W (12)

at the output of the register 29.2.3 - X (12) W (31)

at the output of the register 29.3.1 - X (13) W (11) +

+ X (23) W (12)

at the output of the register 29.3.2 - X (13) W (31)

at the output of the register 29.3.3 - X (13) W (21}

ROM output 34.1 -W (11)

at the output of the multiplier 35.1 - C (11) W (11)

at the output of the adder 36.1 - C (11) W (11)

8th beat.

In trigger 24.3, 0 is written, in trigger 24.1 - 0, in trigger 24.2 - 1. the value X (32) is written to register 23.2, the value W (23) is written to register 25.1; the value W (13) is written to register 25.2; the value of W (32) at the output of the multiplier 26.1 - X (31) W (23) at the output of the multiplier 26.2 - X (32) W (13) at the output of the multiplier 26.3 - X (23) W (32) at the output of the adder 28.1 - X (11) W (21) + + X (21) W (22) + X (31) W (23) С (21) at the output of the adder 28.2 - X (12) W (11) + + X (22) W (12) + X (32) W (13) С (12) at the output of the adder 28.3 - X (13) W (31) + + X (23) W (32)

at the output of the register 29.1.1 - W (11) at the output of the register 29.1.2 - X (11) W (31) + + X (21) W (32)

at the output of the register 29.1.3 - X (11) W (21) + + X (21) W (22)

at the output of the register 29.2.1 - X (12) W (31) + + X (22) W (32)

at the output of the register 29.2.2 - X (12) W (21) + + X (22) W (22)

at the output of the register 29.2.3 - X (12) W (11) + + X (22) W (12)

at the output of the register 29.3.1 - X (13) W (21) + + X (23) W (22)

at the output of the register 293.2 - X (13) W (11) x HX (23) W (12)

at the output of the register 29.3.3 - X (13) W (31) at the output of the register 31.1.1 - C (11) at the output of the register 37.1 - C (11) W (11) at the output of the ROM 34.2 - W (21)

at the output of the multiplier 35.1 - C (21) W (11) at the output of the multiplier 35.2 - C (12) W (11) at the output of the adder 36.1 - C (21) W (11) at the output of the adder 36.2 - C (11) W ( 11) ++ C (12) W (21)

0 9th beat.

In trigger 24.3, 1 is written, in trigger 24.1 - 0, in trigger 24.2 - 0. The value of X (33) is recorded in register 23.3, in value 25.1 is written the value W (33)

5 the value W (23) is written to the register 25.2; the value W (13) is written to the register 25.3 at the output of the multiplier 26.1 - X (31) W (33) at the output of the multiplier 26.2 - X (32) W (23) at the output of the multiplier 26.3 - X (33) W (13)

0 at the output of the adder 28.1 - X (11) W (31) + + X (21) W (32) + X (31) W (33) C (31) at the output of the adder 28.2 - X (12) W (21) + + X (22) W (22) + X (32) W (23) - С (22) at the output of the adder 28.3 - X (13) W (11) +

5 + X (23) W (12) + X (33) W (13) С (13) at the output of the register 29.1.1 - С (21) at the output of the register 29.1.2 - 0 (11) at the output of the register 29.1. 3 - X (11) W (31) + + X (21) W (32)

0 at the output of the register 29.2.1 - C (12)

at the output of the register 29.2.2 - X (12) W (31) +

+ X (22) W (32)

at the output of the register 29.2.3 - X (12) W (21) +

+ X (22) W (22)

5 at the output of the register 29.3.1 - X (13) W (31) + + X (23) W (32)

at the output of the register 29.3.2 - X (13) W (21) + + X (23) L / (22) at the output of the register 29.3.3 - -X (13) W (11) + X (23) W (12 )

0 at the output of the register 31.1.1-С (21) at the output of the register 31.1.2-0 (11) at the output of the register 31.2.1 - 0 (12) at the output of the register 37.1 - C (21) W (11) at the output of the register 37.2 - C (11) W (11) +

5 + C (12) W (21)

at the output of the multiplier 35.1 - C (21) W (11) at the output of the multiplier 25.2 - C (22) W (21) at the output of the multiplier 35.3 - C (13) W (31) at the output of the adder 36.1 - C (31) W ( 11) + O

0 at the output of the adder 36.2 - C (22) W (21) + + C (21) W (11)

at the output of the adder 36.3 - C (13) W (31) + + C (11) W (11) + C (12) W (21) 10th cycle

5 In trigger 24.3, 0 is written, in trigger 24.1 - 1, in trigger 24.2 - 0. At the input of trigger 9.1 appears level 1, the trigger sets to 1, thereby switching the output of register 31.1.3 to the input of switch 30.1.

At the output of the multiplier 26.2 - X (32) W (33)

at the output of the multiplier 26.2 - X (33) W (23)

at the output of the adder 28.2 - X (12) W (31)

+ X (22) W (32) + X (32) W (33) - C (32)

at the output of the adder 28.3 - X (13) W (21)

+ X (23) W (22) + X (33) W (23) C (23)

at the output of the register 29.1.1 - C (31)

at the output of the register 29.1.2 - C (21)

at the output of the register 29.1.3 - C (11)

at the output of the register 29.2.1 - C (22)

at the output of the register 29.2.2 - C (12)

at the output of the register 29.2.3 - X (12) W (31)

-i-X (22) W (32)

at the output of the register 29.3.1 - C (13)

at the output of the register 29.3.2 - X (13) W (31)

+ X (23) W (32)

at the output of the register 29.3.3 - X (13) W (21)

+ X (23) W (22)

at the output of the register 31.1.1 - C (31)

at the output of the register 31.1.2 - C (21)

at the output of the register 31.1, .3 - C (11)

at the output of the register 31.2.1 - C (22)

at the output of the register 31.2.2 - C (12)

at the output of the register 31.3..1 - C (13)

at the output of the register 37.1 - C (31) W (11)

at the output of the register 37.2 - C (22) W (2d)

C (21) W (11)

at the output of the register 37.3 - C (13) W (31)

C (11) W (11) + C (12) W (21) - F (11)

at the output of the multiplier 35.1 - C (11) W {22)

at the output of the multiplier 35.2 - C (32) W (21)

at the output of the multiplier 35.3 - C (23) W (31)

at the output of the adder 36.1 - С (11) W (12) + О

at the output of the adder 36.2 - C (31) W (11)

+ C (32) W (21)

at the output of the adder Зб.З - C (22) W (21)

+ C (21) W (11) + C (23) W (31)

at the output of the device appears

first Fourier coefficient: F (11)

11 beat.

In trigger 24.3, 0. is written in trigger 24.1 -0, in trigger 24.2 - 1. At the output of the multiplier 26.3 - X (33) W (33) at the output of the adder 28.3 - X (13) W (31) + X (23) W (32) + X (33) W (33) - С (33) at the output of the register 29.2.1 - С (32) at the output of the register 29,2.2 - С (22) at the output of the register 29.2.3 - С (12) at the output of the register 29.3.1 - C (23) at the output of the register 29.3.2 - C (13) at the output of the register 29.3.3 - X (13) W (31) + X (23) W (32)

at the output of the register 31.1.1 - С (11) at the output of the register 31.1.2 - С (31) at the output of the register 31.1.3-0 (21) at the output of the register 31.2.1 - С (32) at the output of the register 31.2.2 - C (22) at the output of the register 31.2.3 - C (12) at the output of the register 31.3.1 - C (23) at the output of the register 31.3.2 - C (13)

at the output of the register 37.1 - C (11} W (12) at the output of the register 37.2 - C (31) W (11) + + C (32) W (21)

at the output of the register 37.3 - C (21) W (11) + 5 + C (22) W (21) + C (23) W (31) - F (21)

at the output of the multiplier 35.1 - C (21) W (12) at the output of the multiplier 35.2 - C (12) W (22) at the output of the smart & tel 35.3 - C (33) W (31) at the output of the adder 36.1 - C (21) W (12) + O

0 at the output of the adder 36.2 - C (11) W (12) + + C (12) W (22)

at the output of the adder 36.3 - C (31) W (11) + + C (32) W (21) + C (3; 3) W (31) at the output of the device, the value

5 of the second Fourier coefficient: F (21). 12th beat.

In trigger 24.3, 1 is written, in trigger 24.1 -.0, in trigger 24.2 - 0. At the output of register 29.3.1 - C (33)

0 at the output of the register 29.3.2 - С (23) at the output of the register 29.3.3 - С (13) at the output of the register 31.1.1 - С (21) at the output of the register 31.1.2 - С (11) at the output of the register 31.1. 3 - C (31)

5 at the output of register 31.2.1 - С (12) at the output of register 31.2.2 - С (32) at the output of register 31.2.3 - С (22) at the output of register 31.3.1 - С (33) at the output of register 31.3. 2 - C {23)

0 at the output of the register 31..3.3 - C (13) at the output of the register 37.1 - C (21) W (12) at the output of the register 37.2 - C (11) W (12) + + C (12) W (22) at register output 37.3 - C (31) W (11) +

5 + C (32) W (21) + C (33) W (31) F (31)

at the output of the multiplier 35.1 - C (31) W (12) at the output of the multiplier 35.2 - C (22) W (22) at the output of the multiplier 35.3 - C (13) W (32) at the output of the adder 36.1 - C (31) W ( 12) + O

0 at the output of the adder 36.2 - C (22) W (22) + + C (21) W (12)

at the output of the adder 36.3 - C (13) W (32) + + C (11) W (12) + C (12) W (22) at the output of the device, the value

5 of the third Fourier coefficient: F (31) 13th cycle.

In trigger 24.3, 0 is written, in trigger 24.1 - 1, in trigger 24.2 - 0. At the output of register 31.1.1 - C (31)

0 at the output of register 31.1.2 - С (21) at the output of register 31.1.3 - С (11) at the output of register 31.2.1 - С (22) at the output of register 31.2.2 - С (12) at the output of register 31.2. 3 - C (32)

5 at the output of the register 31.3.1 - C (13) at the output of the register 31.3.2 - C (33) at the output of the register 31.3.3 - C (23) at the output of the register 37.1 - C (31) W (12), at the output Register 37.2 - C (21) W (12) + + C (22) W (22)

at the output of the register 37.3 - C (11) W (12) +

+ C (12) W (22) + C (13) W (32) F (12)

at the output of the multiplier 35.1 - C (11) W (13)

at the output of the multiplier 35.2 - C (32) W (22)

at the output of the multiplier 35.3 - C (23) W (32)

at the output of the adder 36.1 - С (11) W (13) + О

at the output of the adder 36.2 - C (31) W (12) +

+ C (22) W (22)

at the output of the adder 36.3 - C (21) W (12) +

+ C (22) W (22) + C (23) W (32)

the value appears at the output of the device

fourth Fourier coefficient: F (12).

14th beat.

In trigger 24.3, 0 is written, in trigger 24.1 - 0, in trigger 24.2 - 1. At the output of register 31.1.1 - C (11) at the output of register 31.1.2 - C (31) at the output of register 31.1.3 - C (21 ) at the output of the register 31.2.1 - С (32) at the output of the register 31.2.2 - С (22) at the output of the register 31.2.3 - С (12) at the output of the register 31.3.1 - С (23) at the output of the register 31.3. 2 - C (13) at the output of the register 31.3.3 - C (33) at the output of the register 37.1 - C (11) W (1.3) at the output of the register 37.2 - C (31) W (12) + + C (32) W (22)

at the output of the register 37.3 - C (21) W (12) + + C (22) W (22) + C (23) W (32) F (22) at the output of the multiplier 35.1 - C (21) W (13) by output of the multiplier 35.2 - Cf12) W (23) at the output of the multiplier 35.3 - C (33) W (32) at the output of the adder 36.1 - C (21) W {13) + О at the output of the adder 36.2 - C (11) W (13 ) + + C (12) W (23)

at the output of the adder 36.3 - C (31) W (12) + + C (32) W (22) + C (33) W (32) at the output of the device, the value of the fifth Fourier coefficient appears: F (22).

Similarly, at 15, the sixth Fourier coefficient also appears at the output of the device: F (32) - C (31) W (12) + C (32) W (22) + + C (33) W (32)

in step 16 - F (13) the seventh Fourier coefficient,

in step 17, the eighth Fourier coefficient is F (23).

at step 18, the ninth Fourier coefficient is F (33).

Claims (1)

SUMMARY OF THE INVENTION A device for calculating a discrete Fourier transform, comprising a control unit, a clock and N-1 computing modules (N is the conversion size), wherein the ith (I G, N-1) computing module contains a trigger, element I, the first the adder, the first multiplier, the input register, the output register of the EPI MPT 1 IE, the output of which is connected to the clock input of the output register, and the first input of the element And, the output of which is connected to the clock input of the input register, the output of the first multiplier is connected to th input of the first adder, whose output is connected to the data input of the output register whose output is connected to the second input of the first adder (i + 1) -ro computing module, 0 the trigger output is connected to the second input of the And element, the clock input of the trigger is connected to the output of the clock generator, and the second input of the first adder of the first computing module is 5 by the input of the logical zero of the device, the information inputs of the input devices of all computing modules are connected to the information input of the device, characterized in that, with In order to expand the functionality by performing the two-dimensional Fourier transform, a block of constant memory of coefficients is introduced into it, and two computational modules are introduced 5 registers, a second multiplier, a second adder, two control triggers, two buffer register nodes, a switch and a constant memory node of coefficients, the output of the first register being connected to the first input of the second multiplier, the output of which is connected to the first input of the second adder, the output which is connected to the first information input of the switch, the information input of the first node 5 buffer registers, the output of which is connected to the second input of the second adder, the output of the second register is connected to the address input of the constant memory node of the coefficients, the output of which is connected to 0 to the first input of the first multiplier, the second input of which is connected to the information input of the second node of the buffer registers and is connected to the output of the switch, the second information input of which is connected 5 to the output of the second node of the buffer registers, the output of the second register is connected to the second input of the second multiplier, the output of the first control trigger is connected to the input of the operation code of the second adder and the information input of the first control trigger of the (1 + 1) -th computing module, the output of the second the control trigger is connected to the control input of the switch and the information input of the second control trigger5 (1 + 1} and computing module, the outputs of the first and second registers of the 1st computing module are connected to the information the inputs of the first and second registers of the (AND 1) th computing module, the clock inputs of the first and second registers, the first and second control flip-flops, the first and second buffer register nodes of all computing modules are connected to the output of the clock generator, the first address output of the control unit is connected to the address input of the constant memory block of coefficients, the output of which is connected to the information input of the first register of the first computing module, the information input of the second register is orogo connected to the second hell0 the output of the control unit, the first clock output of which is connected to the write enable input of the first registers of all the computing modules, the second, third and fourth clock outputs of the control unit are connected to the information inputs of the trigger, the first and second control triggers of the first computing module, and the unit mode setting input control is the input of the device mode reference. I g Shchig. 1 I Figure 2