SU1211754A1 - Device for calculating inverse matrix - Google Patents

Description

the input of the pulse distributor and the first input of the AND element, the output of which is connected to the clock input of the ring register, the output of the first bit of which is connected to the first input of the third element OR the output of which is connected to the gate inputs of the first and second multiplication units and the control input of the sixth switch, the input which is connected to the output of the sixth memory block, whose address input is connected to the input of the device coefficients, the input of setting the values of the elements of the identity matrix of which is connected to the second information block of the first and second multiplication blocks are connected to the first and second outputs of the sixth switch, respectively; the outputs of the first and second multiplications blocks are connected to the write inputs of the seventh and eighth memory blocks, respectively, the outputs of which are connected to the first and second the information inputs of the second adder gating input and output of which are connected respectively with the output of the fourth element OR and the recording input of the fourth memory block, output v The first bit of the ring register is connected to the first of the fourth OR element, the third bit output of the Ring Register is connected to the first input of the first OR element and is countable to the counter input, the output of which the invention relates to computing technology and can be used in digital computers and homogeneous computing structures.

The aim of the invention is to expand the class of tasks to be solved by ensuring that the inverse matrix for the matrix with the property

, ReA / А + (1) with increasing speed.

The drawing shows the block diagram of the device.

The first input, the second input of the pulse distributor is connected to the second inputs of the third, fourth and second OR elements, the fourth output of the pulse distributor is connected to the write enable input of the first block. the memory and the third input of the third element OR, the fifth output of the pulse distributor is connected to the first input of the fifth element —OR and to the third input of the fourth element OR, the sixth output p the pulse distributor is connected to the second input of the second OR element, the seventh output of the pulse distributor is connected to the fourth input of the third OR element, the control inputs of the first, third and fourth switches and the first control input of the second switch, the eighth output of the pulse distributor is connected to the fourth input of the fourth OR element and the second input of the fifth OR element, the output of which is connected to the gating input of the first calculating unit of the scalar product, the ninth output of the distributor and The pulses are connected to the third input of the first element OR, the second input of the element I is connected to the second control input of the second switch and to the tenth output of the pulse distributor, the output of the fifth memory block is connected to the output of the device.

The device contains an input of matrix A 1, memory block 2, switches 3 and 4, block 5 for calculating scalar product 5, switch 6, memory blocks 7 and 8, switch 9, block 10 for calculating scalar product, switch 11, adder 12 , memory block 13, output code 14, memory block 15, switch 16, multiplication blocks 17

and 18, the inputs for specifying the unit 19 and the initial 20 matrices, the memory blocks 21 and 22, the total 1-1a 23, the memory block 24, the pulse generator 25, the And element

26, the pulse distributor 27, the elements OR 28-32, the ring register 33, the counter 34, the comparison circuit 35, the input of the number of cycles 36 ,. start input 37, input setting the address of the coefficients 38.

The proposed computing device is based on the algorithm for calculating the inverse matrix

A- Me- D

(2)

where matrix A satisfies condition (1).

Numerical analogue (2) has the form

A- Je- Ji-j E-Ata -f- HrA f, .. clt:

"one ., . fN K4.1

-2: HV | ZH) V, (3)

(CI) 0

where E is the identity matrix of the same

size, as the given matrix A, L ° E;

t is an odd number. The interval of the integration interval M and the number of members of the row m for a given precision of the calculation of b for the designed computing device can be preliminarily determined from the relations

(IIAIIN

pi-1 "t + 1

(t + 2)

t-2

BePAI;

(t + O (t + 2-11A11m) m + 2- || AllN 0 ,.

(four)

where 11-11 is any of the generally accepted norms of matrices.

The a (4) m and N found are entered into the device.

Transform (3) to a form suitable for implementation in the device.

and to. r m A At --- r7 a ,, A + a, M ... a „A

If eQ. T) "

where a, (KHl (, 1,2, ..., m).

54

The device works as follows.

In the initial state, the pulse generator 25 does not generate pulses, switch 3 connects the output of memory 2 to the first input of block 5, switch 4 connects the output of memory 2 to the second input of block 5, switch 6 connects the output of block 5 to the memory 8, the switch 16 disconnects the memory block 15 from the inputs of multipliers 17 and 18, the switch 9 connects the output of the memory block 3 to the input of the block 10, and the switch 11 connects the output of the memory block 24 and the input of the adder 12.

The inputs A and 20 receive the given matrix A, the input 30 - the number M,

with M

m +

- 30, where AL - if:

20

the number of cycles, gp is the number of members of the row (3), and the input matrix 19 is the unit matrix E. In the memory block 15, the values of the coefficients a ,, are written

25 l - 2 m

A Start command received at input 37 triggers a pulse generator 25, which advances the unit at the outputs of the distributor 27. The first cycle connects to the first inputs of multiplication blocks 17 and 18 of the coefficients from the memory block 15. The matrices are calculated QQ E and a, A, which are recorded in

35 memory blocks 21 and 22, respectively. On the second cycle, in matrix 23, the matrix 5, aoE + a, A is calculated. which is entered into the memory block 24. By the third cycle, the matrix Sg B is inserted into the adder 12. By the fourth cycle, the matrix A is stored in the memory block 2, the switch 16 connects the coefficients a and a to the inputs of the multiplying blocks 17 and 18. Osu) is honored

 calculating the matrices a and a A, which are entered into the memory blocks 21 and 22, respectively. By the fifth tact in block 5, the matrix 2 is multiplied

AA and the result of the multiplication A is transferred to memory block 8, S is calculated in adder 23, ajE + qjfl and stored in memory f5noKa 24. In the sixth cycle, switch 11 connects the output of block 10 to input 55 of adder 12 , in block 1, the matrix A 5 is multiplied, the result is added in the adder 12. In the seventh clock cycle, the switches 3 and 4

connects the output of memory block 8 to the first and second inputs of block 5, switch 16 connects coefficients about 6 6 and blocks 17 and 18 compute matrices OUE, which are stored in the memory. The switch 6 connects the output of the block 5 to the input of the memory block 7, and the switch 9 the output of the block

7- to block 10. On the eighth cycle in block 5, the matrix is calculated.

8, the accumulator 23 calculates the matrix 5g and B + ao A. In the ninth cycle, the matrix A 5 is calculated, which is summed in the adder 12 with the matrix. At the tenth cycle, the ring register of 33 pulses is turned on, from the first output of which the next pair of coefficients Q J Ch is connected, the corresponding matrices 5e a, F + agA are calculated, which are stored in the memory. By impulse

from the second input, block 5 calculates the matrix, which is entered into

block 7, and adder 23 displays matrix 5, + agA. The impulse from the third output in block-10 calculates the matrix, which in sum- tor 12 is added to the matrix + 5 c, and one is entered into the counter 34.

Subsequently, pulses from the outputs of the ring register 33 appear in the same order as before, sequentially obtaining the corresponding intermediate amounts in the adder 12. The number of cycles of the ring distributor 33 is counted by counter 34. When the number of cycles of the counter coincides with the value of M, the signal with the output of the comparison circuit occurs. The generator 25 stops, the switches come to the initial state, and the result A (2) from the memory block 13 arrives at the output.

Claims (1)

A DEVICE FOR CALCULATING THE REVERSE MATRIX, containing the first and second adders, the first and second blocks of multiplication, characterized in that, in order to expand the class of problems to be solved by providing an inverse matrix for the matrix with the property ReA> 0, ReA = / А + А ^t / ~ with increasing speed, a counter, a comparison circuit, five OR elements, a ring register, a pulse distributor, an AND element, a pulse generator, two blocks for calculating the scalar product, six switches and eight memory blocks are introduced into it, the first the accumulator is made accumulating and the information input of the device is connected to the first information input of the first multiplication unit and the recording input of the first memory block, the output of which is connected to the first information inputs of the first and second switches, the outputs of which are connected to the first and second information inputs of the first unit of calculation of the scalar product, the output which is connected to the information input of the third switch, the first and second outputs of which are connected to the recording inputs of the second and third, respectively memory blocks, the outputs of which are connected respectively to the first and second information inputs of the fourth switch and the second information inputs of the first and second switches, the output of the third memory block is connected to the third information input of the second switch, the output of the fourth switch is connected to the first information input of the second bl how to calculate a scalar product whose output is connected to the first information input of the fifth switch, the second information input of which is connected with the output of the fourth memory block and the second information input of the second scalar product calculation unit, the gating input of which is connected to the output of the first OR element, the first input of the second OR element and the control input of the fifth switch, the output of which is connected to the information input of the first accumulating adder, clock input which is connected to the output of the second OR element, the output of the first accumulating adder is connected to the write input of the fifth memory block, whose read permission input is connected to 1211754> nen with the output of the comparison circuit and the stop input of the pulse generator, the start input of which is connected to the start input of the device, the output of the pulse generator is connected to the clock input of the pulse distributor and the first input of the element And, the output of which is connected to the clock input of the ring register, the output of the first discharge of which is connected to the first input of the third OR element, the output of which is connected to the gating inputs of the first and second multiplication units and the control input of the sixth switch, the input of which is connected to the pole output of the second memory block, the address input of which is connected to the input of setting the device coefficients, the input of setting values of the elements of the unit matrix of which is connected to the first information input of the second multiplication block, the second information inputs of the first and second multiplication blocks are connected respectively to the first and second output of the sixth switch, the outputs of the first and the second multiplication blocks are connected to the recording inputs of the seventh and eighth memory blocks, respectively, the outputs of which are connected to the first and second information inputs and a second adder, whose gate input and output are connected respectively to the output of the fourth OR element and the recording input of the fourth memory block, the output of the second bit of the ring register is connected to the first input of the fourth OR element, the output of the third bit of the circular register is connected to the first input of the first OR element and counted . counter input, the output of which soybean Diven to the first input circuit sravno ^{= -} Nia, the second input of which is connected to the input of reference numbers device cycles, the first, second and third pulse distributor outputs are connected to second inputs respectively of the third, fourth and second OR fourth output the pulse distributor is connected to the recording enable input of the first memory block and the third input of the third OR element, the fifth output of the pulse distributor is connected to the first input of the fifth OR element and to the third input of the fourth of the second OR element, the sixth output of the pulse distributor is connected to the second input of the second OR element, the seventh output of the pulse distributor is connected to the fourth input of the third OR element, the control inputs of the first, third and fourth switches and the first control input of the second switch, the eighth output of the pulse distributor is connected with the fourth input of the fourth OR element and the second input of the fifth OR element, the output of which is connected to the gate input of the first scalar product calculation unit , the ninth output of the pulse distributor is connected to the third input of the first OR element, the second input of the And element is connected to the second control input of the second switch and to the tenth output of the distributor, pulses, the output of the fifth memory block is connected to the output of the device.