SU1681309A1 - Linear convolver - Google Patents

Abstract

The invention relates to computing and can be used in automatic and computing devices to perform linear convolution calculations. The aim of the invention is to increase the speed and economy of equipment by reducing the number of cycles to access the source of operands. This goal is achieved by introducing into the device m one-dimensional digital filters, m delay lines, m-input adder and a control unit containing information about the source of operands 3 of 3 pf files, 5 sludge

Description

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The invention relates to computing and can be used in automatic and computing devices to perform linear convolution calculations.

The purpose of the invention is to increase the speed and economy of equipment by reducing the number of cycles to access the source of operands.

Figure 1 shows the functional diagram of the device; Fig. 2 is a control block diagram; on fig.Z - diagram of the digital delay line; 4 is a diagram of a one-dimensional digital filter (DF); figure 5 - scheme of the m-input adder long.

The device contains a control unit 1, 2.1-2. One-dimensional digital filters, digital delay lines 3.1-3. (T-1), t-input adder 4, output 5 of the clock signal of the sequence of operands X,

input 6 of the sequence of operands X, input 7 of the clock signal of the sequence of operands H, input 8 of the sequence of operands H, output 9 of the query of the next operand X output 10.1 of the query start of the sequence of operands X, address output 10.2, output 11 reset to O and output 12 of the finished result of calculations

The control unit 1 contains a master of the sizes of the matrices of the operands X, made in the form of counters 13 (clock-1 counting states), 14 (per q + 1 counting states). 15 (on p-1 counting states), 16 (on p + 1 counting states), scheme OR 17 scheme NOT 18, scheme OR 19, schemes NOT 20 and 21, and schemes 22 and 23

Each delay line 3 m contains a HE 24 circuit, a counter 25 (for s-p-tn k-1 counting states) and a random access memory (03 V) 26 whose output is the output of the iTi line 3 3

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Each digital filter 2.1-2.t contains n registers 27.1-27.P for operands X, n registers 28.1-28.p for operands H, n multipliers 29.1-29.n, n-input adder 30 and output of adder 30 which serves as an output for a one-dimensional digital filter.

Adder 4 contains m inputs, where, 11 registers 31.1-31.6,32.1-32.3,33.1- 33.2 of the 1st, 2nd and 3rd Rus, respectively, 5 adders 34.1-34.3, 35, 36 of the 1st, 2- first and third Rus, respectively, and output 12, which is also the output of the adder 36 and at the same time the output of the device,

The device works as follows

Known formula for linear two-dimensional convolution

m - 1 p - 1

yst- 2 S hijxs-i.t-j, C1)

I 0 j 0

where hij, xs-i, t-j are the operands X and H of the device.

The internal sum in expression (1) is a one-dimensional linear convolution, and 2.1-2.t digital filters are used to calculate it. To calculate the external sum in expression (1), an rp input adder 4 is used.

To prepare the device for operation, it is necessary to record a sequence of coefficients - the operands H, for this purpose, a sequence of operands H must be input to input 8, followed by clock signals at input 7.

The rate of operation of the device is determined by a clock signal at input 5. After turning on the clock signal at input 5, the device will be ready for operation only after output 10.1 shows a signal to request the start of a sequence of operands X (an exception is the first signal at output 10.1, widened after turning on the clock signal at input 5, it must be skipped, since the device may not be ready).

At the request of the start of a sequence of operands X (output 10.1) at input 6, the first operand of the sequence X - XOQ must be set. After that, at the request of the next operand of the sequence X (output 9), the next operands of the sequence should be sent to input 6

X: xoi, xo2Xpq. Output 12 devices

elements of the sequence of two-dimensional linear convolution appear, yoi ...., ym + q-2, n + p-2, followed by a clock signal at input 5. The delay in the appearance of the element yoi at output 12 relative to the moment of arrival operand xoi to input 6 is determined by the total delay on one one-dimensional digital filter and m-input adder 4

The device operates in a conveyor mode. Upon completion of the convolution of one sequence of operands X, the device is ready to calculate the convolution with another sequence of X operands, so that at output 12 after the last element ym + qi, n + p-2 of one sequence of two-dimensional linear convolution, immediately follows an element of the following sequence of two-dimensional linear convolutions.

After loading the operands of the sequence H, the first digital filter 2.1

5 will be configured to calculate a one-dimensional convolution with a sequence of operands hoo, hoi,. ,,, hon, which is recorded in its registers 28.1-28.p. Accordingly, the second digital filter 2.2 will be configured to calculate the convolution with the sequence

The operands rno, hnhin, and so forth, the m-th digital

2.gp filter - with hmo, hmihmn.

We show that if at the moment of arrival the beginning of the sequence of operands X in

5 of all digital filters, registers 27.1-27. For the sequence of X operands are zero, in all digital delay lines Z. zeros are written, X-matrix operands arrive at each input 6 of the device

0 Х ° - // хц ° //) И), 1m + q-2; j 01n + p-2), which is read from right to left and from top to bottom, with the matrix of operands X located in the upper left corner of the matrix of operands X °, and the remaining elements of the matrix

5 operands X ° are zeros, then the device will calculate the elements of the sequence of a two-dimensional linear convolution. Indeed, let the matrix of operands X ° is already partially read, and the input of the first digital

0 filter 2.1 receives operand Xs, t °, at this moment operand Xs-i, t ° enters the input of the second digital filter 2.2, the third - Xs-2, t °, etc., and the input of the m-th digital cylinder 2 .m - Xs-m + i, t °.

5 Number of digital filters 2.1-2 m

numbers 0.1t-1, we get in accordance

with (1) at the output of the f-ro digital filter, the result of a linear convolution

 hijXs-i, t-j ° (, 1m-1).

These numbers are summed on the t-input adder 4. As a result, at the output of the device, we get the result: elements of the sequence of two-dimensional linear convolution yst by the formula (1).

Control block 1 is designed to form a sequence of a matrix of operands X ° as a result of complementing the sequence of operands of a matrix X

zero mi. Counters 13 and 14 form a column counter of the matrix of operands X °, counters

15 and 16 - row counter of the matrix of operands X °. Counter 14 is in a q + 1 counting state. The logical zero signal at the output of the counter 14, which appears when q + 1-ro reaches the state, through the circuit 22 provides a zero signal

output 11, and also stops passing through the circuit And 23 clock signals from input 5 to output 9 of the request of the next item.

In addition, the signal at the output of the counter

14 is connected to the enable input of the counter 13 and through the circuit NOT 18 to the enable input of the counter 14. Therefore, when it appears, the counter 14 stops,

and counter 13, having t-1 counting states, starts counting and counts t-1 cycles, during which the zero sequence of the last t-1 columns of each row of the X operands matrix is input to the input sequence of operands X of the first digital filter 2.1.

When the 13t-1-state counter reaches the output, a logical zero signal appears at its output, which is transmitted to the output of the OR circuit 17, simultaneously sets the counters 13 and 14 to the initial state and provides, through the HE-21 circuit, the appearance of a positive front the signal at the clock input of the counters 15 and 16, which ensures the transition to the next line.

Similarly, the row counter of the matrix of operands X °, formed by counters 15 and 16, works. Counter 16 has P + 1 counting states and counts the first p rows of the matrix of operands X °. When reaching the P + 1-ro state, the signal at the output of the counter

16, through the circuit, And 22 provides the occurrence of a zero signal at the output 11, and also stops passing the AND 23 clock signals from the input 5 to the output 9 of the request for the next operand. At the same time, the counter 16 also stops, and the counter

15 starts the score. Counter 15, having n-1 counting states, counts n-1 zero rows of the matrix of operands X °. When installing the counter 15 in the n-1-e state, i.e. before the arrival of the first element of the last row of the matrix of operands X °, at the output 10.1 of the query of the start of the sequence of operands X, a logical zero signal appears indicating the request of the first element of the new sequence of operands X.

Thus, before the arrival of the first element of the new sequence of operands X in all digital delay lines

3.1-3, (t-1) and zero elements will be written to all m digital filters, which is necessary for normal operation of the device, and all the counters of control unit 1 will be in their original states.

The states of the counters 16 and 14 are used to control the sampling of the operand of the sequence X: the states of the counter 16 (1,2, ..., p) correspond to the line number, and

counter 14 (1,2q) - number

column of the matrix of operands X, which must at this moment arrive at the input 6 of the sequence of operands X.

Digital delay line Z., shown in FIG. 3, works as follows.

During the positive half cycle of the clock signal, which is inverted by the NOT 24 circuit, the data set at the RAM input is recorded. At the end of the positive half cycle of the clock signal, the value of counter 25 is increased by one and data is read from RAM 26 to a new address. Since counter 25 has s counting states and the counter output is connected to the installation input of the initial state of the counter, the first condition. The data address of RAM 26 is determined by the value of the counter, therefore, the data recorded in RAM 26 is outputted with a delay of s ticks.

Each digital filter 2., t works as in the prototype.

Adder 4 is divided into Russ. But to the first russa, the m input numbers are stored in m registers 31.1-31.6 and summed up in pairs on adders 34.1-34.3, the results of the summation are stored in registers 32.1- 32.2 of the second rus and again in pairs, and so on. On the last 3rd tier, two numbers are summed up (in Fig. 5). If for some number there is no pair, then it is transferred to the next rus register unchanged. To synchronize the operation of all registers of the adder 4, their clock inputs are connected to the input 5 of the clock signal of the sequence of operands X.

Claims (4)

Invention Formula 1, A device for calculating a linear convolution comprising a two-dimensional digital filter, a source of operands, and a control unit, characterized in that. In order to increase speed and save equipment, the control unit contains a matrix size generator, made in the form of four counters, respectively, on m-1, q + 1, n-1 and p + 1 counting states, two AND schemes, two OR schemes and three schemes NOT the clock input of the control unit is connected to the clock inputs of the first and second counters and the first input of the first AND circuit, the output of the first counter is connected to the first input of the first OR circuit, the output of the second counter is connected to the input of the first NOT circuit, the second input of the first OR circuit, the first input of the second AND circuit and the counting input of the first counter, the output of the third counter is connected to the first input of the second OR circuit, the output of the fourth counter is connected to the input of the second NOT circuit, the second input of the second OR circuit, the second input to The gate of the AND circuit and the resolution enable input of the third counter, the output of the first circuit OR is connected to the input of the third circuit NOT and the inputs of the initial installation of the first and second counters, the output of the third circuit is NOT connected to the clock inputs of the third and fourth counters, the output of the first circuit is NOT connected to the resolution input the second counter, the output of the second circuit is NOT connected to the resolution enable input of the fourth counter, the output of the second circuit OR is connected to the inputs of the initial installation of the third and fourth counters and is the output of On the beginning of the sequence of operands X of the control unit, the output of the second AND circuit is connected to the second input of the first AND circuit and is the zero output, the output of the first AND circuit is the output of the next operand request of the X sequence, and the output outputs of the second and fourth counters are output addresses of operands X, 2. The device according to claim 1, that is, with the fact that the two-dimensional digital filter is made in the form of one-dimensional m digital filters, t-1 digital delay lines on s p + nk-1 cycles, where k is the number of delay cycles of a sequence X in digital filters, and an m-input adder, the device input for operands X is the input sequence of operands X of the first digital cylinder, the device input for operands H is the input of operands of the sequence H m-th digital filter, all digital filters are connected in series ak. that the output of the sequence of operands X of the previous digital filter is connected to the input of the sequence of operands X of the next digital filter via a digital delay line, and the output of the sequence of operands H of the next digital filter is connected to the input of the sequence of operands N of the previous digital filter, the output of each digital filter on which appears the result of the convolution is connected to the corresponding input of the m-input adder, the output of the m-input adder is the output of the device, the input of the clock signal the sequence of operands N is connected to the clock inputs of the sequence of operands N of all digital filters, the clock input of the sequence of operands X is connected to 0 input clock signal sequence of the operands X of each digital filter, the input clock signal of each digital delay line, clock input rn-input adder and the input input 5 of the control unit, the output of the zeroing of the control unit is connected to the input of the zeroing of the first digital filter, the output of the request for the start of the sequence of operands X, the output of the request for the next element 0 sequences of operands X and address outputs of the second and fourth counters of the control unit are connected to the sources of the device operands, 3. The device pop. 1, which differs - 5 with the fact that the digital delay line contains a counter on p + nk-1 counting states, a random access memory (RAM) and a NOT circuit, the clock input of the digital delay line is connected to the circuit input NOT, the circuit output is NOT connected to the clock input of the counter, and the read / write RAM, the output of the counter is connected to the address input of the RAM, the output of the transfer of the counter is connected to the input of the default setting of the counter, the input of the digital delay line is connected to the input of the RAM data, the output of the data RAM is the output of the digital delay line. 4. Device pop. 1, distinguishing the group-e-0 with the fact that the one-dimensional digital filter contains n registers connected in series for sequences of operands X and H, the inputs of the first registers are connected to the inputs 5 sequences of operands X and H digital filter, respectively, p multipliers, the first inputs of which are connected to the outputs of the corresponding registers of the sequence of operands X, and the second 0 inputs are connected to the outputs of the registers of the operands H in the reverse order, a p-input adder, to the inputs of which the outputs of the multipliers are connected, and the output is connected to the digital output 5 filters are additionally connected to a clock input of a sequence of operands H of a digital filter — clock inputs of registers of a sequence of operands H, with a clock input of a sequence of operands X of a digital filter — clock echoes of registers of a sequence of operands X and an n-input adder, with an output of a sequence of operands H of a digital filter last register output by u ff 2.2 i i i i i i Mr ik 4 2./72 1m the sequence of operands H, with the output of the sequence of operands X of the digital filter - the output of the last register of the sequence of operands X. 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