RU2179333C1 - Synergistic computer system - Google Patents

Abstract

FIELD: computer engineering; high-capacity computer systems. SUBSTANCE: system designed for solving problems whose algorithms admit multisequencing at command level has N functional units and "each-with-each" switch; each functional unit has control device, command memory device, and operating device; the latter has input/output device and/or arithmetic-logic device, and/or data memory device. EFFECT: enhanced capacity of computer system. 4 dwg, 1 tbl

Description

 The invention relates to computer technology and can be used in the construction of high-performance computing systems to solve problems whose algorithms allow parallelization at the command level.

 A device is known, the microprocessor IA-64 (see Shakhnovich I. The present and the next century. - J. Electronics: Science, Technology, Business, N 6, 1999, pp. 8-11), which implements parallelism at the command level using the concept "long command word." The device consists of a cache of instructions of the 1st level, a cache of data of the 1st level, a common cache of the 2nd and 3rd levels, a control device, a file of specialized registers: integers, floating point, branching and predicates There are four types of functional device groups: four integer arithmetic devices, two floating point operations devices, three branch devices, one data memory access device. Functional devices are managed centrally using long command words of a fixed size, each of which contains three simple commands that define the operations of three different functional devices. The sequence of simple commands in the word, as well as the relationship between words, is determined by the mask field in the word.

The disadvantages of this device are:
additional memory costs for program code caused by a fixed size of the control word;
suboptimal use of functional devices and, as a result, reduced performance due to an imbalance in the number of functional devices and the number of simple commands in a command word, specialization of functional devices and registers, mismatch in the capacity of a functional memory device (maximum one number per clock) with the capabilities of functional devices of integer operations and floating point operations.

 A device is also known, the E2K microprocessor (see Kuzminsky M. Domestic microprocessors: Elbrus 2K - Open Systems, N 5-6, 1999, pp. 8–13), using the same concept of a “long command word” to implement parallelism. The device consists of a cache of the 1st level, a cache of data of the 1st level, a general cache of the 2nd level, a pre-paging buffer, a control device, a file of universal registers and a group of similar functional devices based on arithmetic logical devices (ALU) and combined into two clusters. The length of the command word that controls the operation of functional devices is variable.

 The disadvantages of this device include a decrease in device performance when reloading the cache of level 1 commands due to a mismatch between the speed of fetching commands and the speed of filling it, as well as the widespread use of data in the shared cache of level 2 and / or RAM.

 The closest, in technical essence and the achieved result to the claimed device, is the electronic computer QA-2 (Computers on VLSI, Book. 1, Trans. From Japanese. Motoska T., Tomita S., Tanaka H., etc. - M.: Mir, 1988, pp. 65-66, 155 - 158 - prototype). This device consists of a control device, a unit of collective specialized registers, a switching network, N similar functional devices (in the described specific implementation of the prototype N = 4), built on the basis of universal arithmetic-logic devices. The switching network is implemented on the principle of "each with each", has N inputs, 2N outputs and provides a direct connection of the output of any arithmetic-logic device with the inputs of other arithmetic-logic devices.

 Device management is centralized. A long command word, of a fixed size, contains four fields (simple commands) for controlling arithmetic and logic devices, a field for accessing four different banks of the main memory, and a field for controlling the sequence of simple commands. Simple commands contain information about the code of the operation to be performed, the length of the operands, the address of the source registers of the left and right operands of the arithmetic logic device, and the address of the destination registers.

 The disadvantages of the known computers are as follows. A fixed length of the control word leads to non-optimal use of memory resources, namely, the field is present in the command word regardless of whether or not the corresponding arithmetic-logical device is used. The inability to directly receive data from the memory by arithmetic-logic devices, since the data must be pre-recorded in the collective register block, reduces the performance of the device.

 The objective of the invention is to increase the performance of a computing system.

 The problem is solved in that in the proposed synergistic computer system containing N functional blocks, the switch "each with each", having N information inputs, 2N address inputs and 2N information outputs, according to the invention, each functional block contains a control device, a command memory device and an operating device that implements double and single operations, and also has two information inputs, two address outputs and one information output. The first information input of the k-th functional unit (k = 1, ..., N) is connected to the (2k - 1) -th information output of the switch, the second information input is connected to the 2k-m information output of the switch, the first address output is connected to ( 2k - 1) -th address input of the switch, the second address output is connected to the 2k-th address input of the switch, the information output of the k-th functional block is connected to the k-th information input of the switch.

 The information inputs of the functional block are the information inputs of the control device, the address outputs of the functional block are the first and second address outputs of the control device, the third address output of the control device is connected to the address input of the command memory device, the command input / output of the control device is connected to the command input / output of the device command memory, the control output of the control device is connected to the control input of the operating device, the first and second the information outputs of the control device are connected respectively to the first and second information inputs of the operating device, the information output of the operating device is the information output of the functional unit.

 The operating device comprises an input / output device and / or an arithmetic logic device and / or a data memory device, the first information input of the operating device being an information input of an input / output device, an arithmetic logic device and a data memory device, the second information input of the operating device is the address input of the input-output device and the data memory device and the second information input of the arithmetic logic device, the control input of the operating device tripod is the control input of the input-output device, the arithmetic-logical device and the data memory device, the information output of the input-output device, the arithmetic-logical device and the data memory device is the information output of the operating device.

 Signs in the indicated relationship in the process of conducting a search for novelty were not found, are significant and, together, provide an increase in system performance. This is achieved as follows. Introducing functional blocks into the synergistic computing system that implement data input-output and write-read operations, connecting them to the switch in the same way that other system blocks are connected, eliminates the intermediate information medium in the form of a register file and, accordingly, reduces data access time and also increase, due to the redistribution of blocks within the system, the flow of data received for processing to a volume that ensures the maximum possible load of functional blocks of the system Topics algorithm based on the characteristics of the problem solved and hardware limitations on the number of functional blocks.

 Decentralization of control in a synergistic computer system and, as a result, the inclusion in the structure of functional blocks of the control device and the memory device of commands connected in this way, as well as distributed control of the switch through address inputs connected to the address outputs of the control device, eliminates delays in the computing process, associated with reloading program code. This is achieved by the fact that in the proposed decentralized system, the length of the command word is sharply reduced. So, for a system consisting of 16 functional blocks, the length of the control word for the vast majority of operations will be 16 bits, which is several times less than the length of a simple command for the prototype. Accordingly, the need for instruction cache disappears. The required rate of receipt of the command words can be implemented, for example, by the parallel access method, providing simultaneous reading of the sequence of command words.

 In addition, it should be noted that the unification of intra-system inter-unit communications, as well as the possibility of including various functional blocks in the system according to the set of operations being implemented, makes it possible to optimize the volume of hardware in terms of specific applications for specialized systems in terms of overall mass characteristics and power consumption.

 In FIG. 1 is a structural diagram of a synergistic computing system; in FIG. 2 - the main formats of command words; in FIG. 3 - information graph of the formula (1) in tier-parallel form; in FIG. 4 is an information graph of formula (2) in a tiered-parallel form.

A synergistic computing system (Fig. 1) contains functional blocks 1.1, ..., 1.k, ..., 1.N, a switch 2 of the type "each with each", with N information inputs i ₁ , ..., i _k , ..., i _N , 2N address inputs a ₁ , a ₂ , ..., a _2k-1 , a _2k , ..., a _2N-1 , a _2N , 2N information outputs o ₁ , o ₂ , ..., o _2k-1 , o _2k,. .., o _2N-1 , o _2N . Each functional block consists of a control device 3, a command memory 4 and an operating device 5 that implements double and single operations, and also has two information inputs I ₁ and I ₂ , two address outputs A ₁ and A _2, and one information output O. The information input I _{1 of the} k-th functional block (k = 1, ..., N) is connected to the information output o _{2k-1 of the} switch, the information input I _{2 is} connected to the information output o _{2k of the} switch. The address output A _{1 is} connected to the address input a _{2k-1 of the} switch, the address output A _{2 is} connected to the address input a _{2k of the} switch, the information output O of the kth function block is connected to the information input i _{k of the} switch. The information inputs of the functional block are the information inputs of the control device 3, the address outputs of the functional block are the first and second address outputs of the control device 3, the third address output of the control device 3 is connected to the address input of the command memory 4, the command input-output of the control device 3 is connected to command input-output device memory commands 4, the control output of the control device 3 is connected to the control input of the operating device 5, the first and the second information outputs of the control device are connected, respectively, with the first and second information inputs of the operating device 5, the information output of the operating device 5 is the information output of the functional unit. The operating device 5 comprises an input / output device 5.1 and / or an arithmetic logic device 5.2 and / or a data memory device 5.3, the first information input of the operating device 5 being an information input of an input / output device 5.1, an arithmetic logic device 5.2 and a data memory device 5.3, the second information input of the operating device 5 is the address input of the input / output device 5.1 and the data memory device 5.3 and the second information input of the arithmetic logic device 5.2, controlling input operating unit 5 is a control input of the input-output device 5.1, the arithmetic-logic unit and memory devices 5.2 5.3 Data, information output of input-output devices 5.1, ALU 5.2 and 5.3 the data storage device is a data output of the operating device 5.

 A synergistic computing system operates as follows.

 The initial state of the command memory device, the data memory device is entered from the blocks realizing the input-output operations, and is a sequence of command words and data words, respectively.

Command words (Fig. 2) have two formats. The first format contains an operation code field and two fields with argument addresses. The second format consists of an operation code field, a field with the address of the argument, and a field with the address of the command, number, or subscriber. The size of the operations code field is determined by the nomenclature of operations and must be at least] log ₂ P [binary digits, where P is the number of operations. The size of the fields with the addresses of the argument depends on the number of function blocks and must be at least] log ₂ N [each. The size of the field with the address of the command, number, or subscriber is determined by the maximum amount of addressable command or data memory, or by the number of external subscribers.

 The capacity of the data is determined by the specific implementation of the system, namely the requirements for the type, form and accuracy of the data presentation.

All functional blocks of a synergistic computing system work in parallel and independently from each other, in accordance with the programs located in their instruction memory devices. Each command implements a two-place or one-place operation, which performs a certain integer number of cycles and, upon completion, the result is sent to switch 2. To execute the next command, the control unit 3 of the function block selects the next command word from the command memory 4, unpacks it, generates it in accordance with the operation code, the control signals for the operating device 5 selects the argument addresses from the corresponding fields. Addresses A ₁ and A ₂ at the corresponding address outputs arrive at switch 2.

 Switch 2 makes a direct connection of the first and second information inputs of the functional block with the outputs of the functional blocks, the numbers of which are received by the switch 2, respectively, at the first and second address inputs and ensures the transfer of information from the outputs of the functional blocks to the information inputs. The obtained information is used by the next command as arguments when the operating device 5 implements a double or single operation. The address of a command, number or subscriber selected from format 2 commands is processed directly by the control device when implementing individual control transfer commands, reading or writing numbers, and also input / output commands.

Информационные графы, описывающие последовательность выполнения операций в формулах и их параллелизм, представлены в виде ярусно-параллельных форм на фиг. 3.4.Consider the work of a synergistic computing system, using two formulas as an example:

Information graphs describing the sequence of operations in the formulas and their parallelism are presented in the form of tiered-parallel forms in FIG. 3.4.

 For definiteness, we assume that a synergistic computing system has 16 functional blocks. Of these, 7 blocks, with numbers from 1 to 7, as part of the operating device have only data memory. Blocks 8 to 15 are purely computational, that is, as part of the operating device, they have only an arithmetic-logical device. Block 16 is an I / O block.

 Memory blocks implement read (th) and write (zp) commands of format 2 and have a duration of one clock cycle. A read command is a one-place operation that selects a number from the data memory at the address specified in the command word. The write command implements a two-place operation, the first argument of which is the number coming from the switch, and the second is the address at which this number is written to the data memory specified in the command word.

 Computing blocks implement the following commands: addition (+) and subtraction (-), 1 cycle long; multiplication (*), duration 2 cycles; division (/), lasting 4 steps. All commands of the computing unit have the first format, implement double-place operations, and the subtracted and divisible are specified in the first address.

 To ensure coordinated interaction of blocks, when there is a need to delay the result of execution at the output of a functional block, the "waste" (t) command of the second format is used, which stores the state of the t-cycle block. You can also save the result by one clock by organizing a record in the working cell of the data memory. The recorded number, at the end of the operation, is not only entered into the data memory, but also fed to the output of the function block. When performing multi-cycle operations, the result of the previous operation is stored at the output of the function block, until the last measure of the current operation.

Формат 2

или

или

где <мнемокоп> - условное обозначение кода операции; <номер> - число от 1 до 16, указывающее номер функционального блока, результаты которого используются в качестве аргумента при выполнении операции; <имя> - наименование аргумента, адрес которого (после трансляции и загрузки программ) будет сформирован в поле адреса числа.We will take the following form of writing command words:
Format 1

Format 2

or

or

where <nemocop> is the symbol of the operation code; <number> - a number from 1 to 16, indicating the number of the function block, the results of which are used as an argument when performing the operation; <name> - the name of the argument whose address (after broadcasting and downloading programs) will be generated in the address field of the number.

 In the "waste" commands, a number is written in the place of names.

We place the matrix elements (a ₁₁ , a ₁₂ , a ₁₃ , a ₂₁ , a ₂₂ , a ₂₃ , a ₃₁ , a ₃₂ , a ₃₃ ) in columns in memory blocks 1-3. The vectors (b ₁ , b ₂ , b ₃ ) and (c ₁ , c ₂ , c ₃ ) are element-wise in memory blocks 4-6. Variables e, z, v in the fourth memory block. Variables d, y in the fifth and sixth blocks, respectively. Variables x, w in the seventh block of memory.

When programming, to save intermediate results, we introduce additional operands, namely the working cells r ₁ and r ₃ in the seventh functional block. To save the result by one cycle with the simultaneous release of the computing unit, we introduce a fictitious operand r ₂ in the fourth block. Writing to this cell is performed, but the recorded result is not used further.

 The results of programming the function blocks when calculating these formulas are presented in the table.

 The last row of the table shows the number of commands executed by each function block.

Claims (1)

 A synergistic computing system containing N functional blocks, an "each with each" switch having N information inputs, 2 N address inputs and 2 N information outputs, characterized in that each functional block consists of a control device, a command memory device and an operating device, implements double and single operations, and also has two information inputs, two address outputs and one information output, and the first information input of the k-th functional block (k = 1, ..., N) is connected to (2k-1) the information output of the switch, the second information input is connected to the 2k information output of the switch, the first address output is connected to the (2k-1) address of the switch, the second address output is connected to the 2k address of the switch, the information output is k of the functional block is connected to the kth information input of the switch, the information inputs of the functional block are the information inputs of the control device, the address outputs of the function block are respectively the first and second address moves of the control device, the third address output of the control device is connected to the address input of the command memory device, the command input / output of the control device is connected to the command input / output of the command memory device, the control output of the control device is connected to the control input of the operating device, the first and second information outputs of the device control are connected respectively to the first and second information inputs of the operating device, the information output of the operating device is is the information output of the functional block, and the operating device contains an input-output device, and / or an arithmetic logic device, and / or a data memory device, the first information input of the operating device being the information input of an input-output device, arithmetic logic device, and device data memory, the second information input of the operating device is the address input of the input-output device and the data memory device and the second information input of the arithmetic log device, the control input of the operating device is the control input of the input-output device, the arithmetic logic device and the data memory device, the information output of the input-output device, the arithmetic logic device and the data memory device is the information output of the operating device.

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