RU2292075C1 - Synergetic computing system - Google Patents

Abstract

FIELD: computer engineering; can be used in creation of high-performance computing systems for task handling, algorithms of which allow parallelization on command level.

SUBSTANCE: device contains N functional units, intermeshed commutator, resource analyzer, which contains registers blocks, memory blocks, AND elements blocks, counters, multiplexing units, synchronizing generator, control device, and comparison scheme.

EFFECT: increased reliability.

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Description

The invention relates to computer technology and can be used in the construction of high-performance computing systems (AC) to solve problems whose algorithms allow parallelization at the command level.

The satisfaction of the need for computing resources in solving complex economic problems is ensured by simultaneously reducing the cost of computing resources and building an aircraft with a large number of processors to achieve high and ultra-high performance. The concept of metacomputing, including involving the computing resources of the Internet to solve resource-intensive tasks, is becoming increasingly widespread. The specialized literature describes many algorithms dedicated to solving the problem of constructing high-performance aircraft [1, 2, 3, 4]. However, a common drawback of the algorithms presented in the specialized literature on solving the problem of constructing high-performance aircraft is the lack of a description of the technical implementation: the description of the algorithms is given only at a conceptual level.

A high-performance device, the IA-64 microprocessor [5], which implements parallelism at the command level using the concept of a "long command word", is also known from the literature.

Functional devices in the IA-64 microprocessor are controlled centrally using long, fixed-sized command words, each of which contains three simple commands that define the operations of three different functional devices. The sequence of simple commands in a word, as well as the relationship between words, is determined by the mask field in the word.

The disadvantages of this device are: additional memory costs for program code caused by a fixed size of the control word; suboptimal use of functional devices and, as a result, reduced performance due to an imbalance in the number of functional devices and the number of simple commands in a command word, specialization of functional devices and registers, mismatch in the capacity of a functional memory device (maximum one number per clock) with the capabilities of functional devices of integer operations and floating point operations.

Also known is a device, an E2K microprocessor [6], using the same concept of a "long command word" to implement parallelism. The device consists of a cache of the 1st level, a cache of data of the 1st level, a general cache of the 2nd level, a pre-paging buffer, a control device, a file of universal registers and a group of similar functional devices based on arithmetic logical devices (ALU) and combined into two clusters. The length of the command word that controls the operation of functional devices is variable.

The disadvantages of this device include a decrease in device performance when reloading the cache of level 1 commands due to a mismatch between the speed of fetching commands and the speed of filling it, as well as the widespread use of data in the shared cache of level 2 and / or RAM.

Also known electronic computer QA-2 [7]. This aircraft consists of a control device, a unit of collective specialized registers, a switching network, N similar functional devices (in the described specific implementation of the prototype N = 4), built on the basis of universal arithmetic-logic devices. The switching network is implemented on the principle of "each with each", has N inputs, 2 N outputs and provides a direct connection of the output of any arithmetic-logic device with the inputs of other arithmetic-logic devices.

Aircraft management is centralized. A long command word, of a fixed size, contains four fields (simple commands) for controlling arithmetic and logic devices, a field for accessing four different banks of the main memory, and a field for controlling the sequence of simple commands. Simple commands contain information about the code of the operation to be performed, the length of the operands, the address of the source registers of the left and right operands of the arithmetic logic device, and the address of the destination registers.

The disadvantages of the known aircraft are the following:

- a fixed length of the control word leads to non-optimal use of memory resources, namely, the field is present in the command word regardless of whether or not the corresponding arithmetic-logical device is used;

- the inability to directly receive by the arithmetic-logic devices data coming from the memory, since the data must be pre-recorded in the block of collective registers, leading to a decrease in device performance;

- low aircraft performance.

The closest, in technical essence and the achieved result to the claimed device, is a synergistic computing system (SHS) [8], which is a prototype of the claimed device and contains N functional blocks, a switch "each with each", having N information inputs, 2 N address inputs and 2 N information outputs, each functional block consists of a control device, a command memory device and an operating device that implements double and single operations, and also has two information inputs yes, two address outputs and one information output, the first information input of the K-th functional block (K = 1, ..., N) connected to the (2K-1) -th information output of the switch, the second information input connected to 2K- m information output of the switch, the first address output is connected to the (2K-1) -m address input of the switch, the second address output is connected to the 2K-m address input of the switch, the information inputs of the function block are information inputs of the control device, the address outputs of the function block are Responsibly the first and second address outputs of the control device, the third address output of the control device is connected to the address input of the command memory device, the command input / output of the control device is connected to the command input / output of the command memory device, the control output of the control device is connected to the control input of the operating device, the first and the second information outputs of the control device are connected to respectively the first and second information inputs of the operating device, information The output of the operating device is the information output of the functional unit, and the operating device contains an input / output device and / or an arithmetic logic device and / or a data memory device, the first information input of the operating device being an information input of an input / output device, arithmetic logical device and data memory device, the second information input of the operating device is the address input of the input-output device and the data memory device and W eye data input of the arithmetic logic unit, the control input of the operating device is a control input of input-output devices, an arithmetic logic unit and a memory device data information output of input-output devices, an arithmetic logic unit and a memory device data is data output of the operating device.

The simplicity of interprocessor communications, decentralization of control and the possibility of operational reconfiguration of the structure are the fundamental principles for building high-performance, multiprocessor, fault-tolerant aircraft.

The first two principles are implemented in the prototype. The third principle - the operational reconfiguration of the structure - is impossible to implement within the framework of the well-known unreserved SHS.

The disadvantages of the known SHS are the low reliability of operation and the lack of the ability to reprogram the course of the computing process in case of failure of one or more functional blocks. Indeed, a structural calculation of the reliability of the known SHS shows that if one of the N functional blocks fails, the entire system will fail, that is, from the point of view of the reliability of functioning, the known SHS represents a series connection of functional blocks. The probability of failure-free operation of the known SHS is equal to the product of the probabilities of failure-free operation of the functional blocks included in the SHS.

The figure 1 shows graphs of the dependence of the uptime of a known SHS on the number of functional units and the probability of their uptime.

The analysis of figure 1 shows that from the point of view of reliability of operation, the known SHS works inefficiently. Known SHS is unrecoverable.

Therefore, the disadvantage of the known SHS is, according to the authors of the present invention, the low reliability of SHS.

The present invention is aimed at improving the reliability of the SHS by eliminating the failure of the functional unit and automatically transfer the system to a healthy state. In this case, of course, the performance of the SHS and the effectiveness of solving the problem are reduced.

To obtain a technical result in a SHS containing N functional blocks, an “each with each” switch having N information inputs, 2 N address inputs and 2 N information outputs, each functional block consisting of a control device, a command memory device, and an operating device that implements double and single operations, and also has two information inputs, two address outputs and one information output, the first information input of the K-th functional block (K = 1, ..., N) connected to (2K-1) - m infor each switch each output, the second information input is connected to the 2Kth information output of the switch each "each", the first address output is connected to the (2K-1) -m address input of the switch "each with each", the second address output connected to the 2Kth address input of the switch "each with each", the information inputs of the functional block are the information inputs of the control device, the address outputs of the functional block are the first and second address outputs of the control device, third the th output address of the control device is connected to the address input of the command memory device, the command input-output of the control device is connected to the command input / output of the command memory device, the control output of the control device is connected to the control input of the operating device, the first and second information outputs of the control device are connected respectively to the first and second information inputs of the operating device, the information output of the operating device is the information output of the function unit, and the operating device comprises an input / output device, and / or an arithmetic logic device, and / or a data memory device, the first information input of the operating device being an information input of an input / output device, an arithmetic logic device, and a data memory device, the second information input of the operating device is the address input of the input-output device and the data memory device and the second information input of the arithmetic logic device controlling the input the operating device is the control input of the input-output device, the arithmetic-logical device and the data memory device, the information output of the input-output device, the arithmetic-logical device and the data memory device is the information output of the operating device, a resource analyzer is introduced having N information inputs and a control input, N information outputs and control output, and (1, ..., N) the information inputs of the resource analyzer are connected respectively to the information outputs by the odes (1, ..., N) of the functional blocks, the information outputs (1, ..., N) of the resource analyzer are connected respectively to the information inputs (1, ..., N) of the "each with each" switch, the control output of the analyzer resources is connected to the control input of the switch "each with each", and the control input of the resource analyzer is the input of a synergistic computer system, while the resource analyzer contains series-connected registers of the first block of registers, memory modules of the first memory block, elements of the block of elements AND, first th counter, multiplexers of the first block of multiplexers and memory modules of the second block of memory, series-connected registers of the second block of registers, a comparison circuit, a control device and multiplexers of the second block of multiplexers, series-connected clock and second counter, as well as multiplexers of the third block of multiplexers, the first inputs of the registers the first block of registers are connected to the information inputs of the resource analyzer, the second inputs of the registers of the first block of registers are connected to the second output of the clock, the second information inputs of the memory modules of the first memory block are connected to the information inputs of the resource analyzer, the third inputs of the memory modules of the first memory block are connected to the third output of the clock, the fourth output of which is connected to the first inputs of the registers of the second block of registers, the second inputs of which are connected to the outputs memory modules of the first memory block, the outputs of the registers of the first block of registers are connected to the second, inverse inputs of the elements of the block of elements And and with the second the control device, the output of the comparison circuit is connected to the second input of the second counter, the outputs of which are connected to the second inputs of the multiplexers of the first block of multiplexers, the control inputs of which are connected to the output of the control device, the third input of the control device is connected to the first output of the clock generator, the fourth input of the control device is an input synergistic computing system, the information inputs of the multiplexers of the second block of multiplexers are connected to the outputs of the memory modules of the second memory block, the outputs of the multiplexers of the second block of multiplexers are connected to the second information inputs of the memory modules of the second memory block, the output of the control device is connected to the third control inputs of the memory modules of the second memory block and the control inputs of the multiplexers of the third block of multiplexers, the information inputs of the multiplexers of the third block of multiplexers are connected to the information the inputs of the resource analyzer, the outputs of the multiplexers of the third block of multiplexers are information output outputs of the resource analyzer, the output of the control device is the control output of the resource analyzer.

The introduced analyzer of resources and communications ensures the achievement of a technical result: improving the reliability of the functioning of the known SHS.

The figure 2 shows the structural diagram of the proposed SHS.

The figure 3 shows the structural diagram of the resource analyzer of the proposed SHS.

The figure 4 shows a block diagram of the algorithm of the proposed SHS.

The figure 5 shows a block diagram of the algorithm of the analyzer of the resources of the proposed SHS.

The figure 6 shows the graph of the proposed SHS in normal mode of operation.

The figure 7 shows the graph of the proposed SHS in the operating mode with one idle functional unit.

The figure 8 shows the formats of the SHS commands.

The figure 9 shows the graphs of the uptime of the proposed SHS from the number of faulty functional blocks.

The analysis of figures 2, ..., 9 shows that, in the event of a functional block failure, the proposed SHS remains operational. Indeed, in the event of a functional unit failure, the proposed SHS switches to a more intense mode of operation, in which, having fewer resources, the SHS performs specified, initial functions. This is the fundamental difference between the proposed SHS from the known SHS. The introduction of a resource analyzer and associated relationships allowed the implementation of the reconfiguration of SHS resources.

The proposed SHS (Figure 2) contains N functional blocks 1.1, ..., 1.i, ..., 1.n, a switch 2 "each with each", a control device 3, a command memory 4, an operating device 5, input-output device 5.1, arithmetic logic device 5.2, data memory device 5.3, resource analyzer 6, control, input 7. Switch 2 "each with each" has N information inputs, 2 N address inputs and 2 N information outputs. Each functional block 1.1, ..., 1.i, ..., 1.n consists of a control device 3, a command memory 4 and an operational device 5 that implements double and single operations, and also has two information inputs, two address output and one information output. The operating device 5 comprises an input / output device 5.1, and / or an arithmetic logic device 5.2, and / or a data memory device 5.3. The first information input of the Kth functional block 1.k (K = 1, ..., N) is connected to the (2K-1) th information output of the switch 2 "each with each". The second information input of the Kth functional block 1.k (K = 1, ..., N) is connected to the 2Kth information output of the switch 2 "each with each". The first address output of the Kth functional block 1.k (K = 1, ..., N) is connected to the (2K-1) th address input of the switch 2 "each with each". The second address output of the Kth functional block 1.k (K = 1, ..., N) is connected to the 2Kth address input of the switch 2 "each with each". The information inputs of the functional block 1.1, ..., 1.i, ..., 1.n are the information inputs of the control device 3. The address outputs of the functional block 1.1, ..., 1.i, ..., 1.n are respectively, the first and second address outputs of the control device 3. The third address output of the control device 3 is connected to the address input of the command memory device 4. The command input-output of the control device 3 is connected to the command input / output of the command memory 4. The control output of the control device 3 is connected to control input operation device 5. The first and second information outputs of the control device 3 are connected respectively to the first and second information inputs of the operating device 5. The information output of the operating device 5 is the information output of the functional unit 1.1, ..., 1.i, ..., 1. n The first information input of the operating device 5 is the information input of the input-output device 5.1, arithmetic logic device 5.2 and data memory device 5.3. The second information input of the operating device 5 is the address input of the input / output device 5.1 and the data memory device 5.3 and the second information input of the arithmetic logic device 5.2. The control input of the operating device 5 is the control input of the input-output device 5.1, arithmetic logic device 5.2 and data memory device 5.3. The information output of input / output device 5.1, arithmetic-logical: device 5.2 and data memory device 5.3 is the information output of operating device 5. Resource analyzer 6 has N information inputs and a control input, N information outputs and a control output. In this case (1, ..., N), the information inputs of the resource analyzer 6 are connected respectively to the information outputs (1, ..., N) of the functional blocks 1.1, ..., 1.i, ..., 1.n. The information outputs (1, ..., N) of the resource analyzer 6 are connected respectively to the information inputs (1, ..., N) of the switch 2 "each with each". The control output of the resource analyzer 6 is connected to the control input of the switch 2 "each with each". The control input of the resource analyzer 6 is the input of a synergistic computing system.

The resource analyzer 6 of the proposed SHS (Figure 3) contains serially connected registers of the first block of registers 9.1, ..., 9.i ..., 9.n, memory modules of the first memory block 10.1, ..., 10.1 ..., 10.n, the elements of the block of elements And 11.1, ..., 11.i ..., 11.n, the first counter 14, the multiplexers of the first block of multiplexers 17.1, ..., 17.i ..., 17.n and memory modules of the second memory block 19.1, ..., 19.i ..., 19.n. The resource analyzer 6 of the proposed SHS contains serially connected registers of the second block of registers 12.1, ..., 12.i ..., 12.n, a comparison circuit 13, a control device 16 and multiplexers of the second block, multiplexers 18.1, ..., 18. i ..., 18.n. The resource analyzer 6 of the proposed SHS contains series-connected clock generator 8 and the second counter 15. The resource analyzer 6 of the proposed SHS contains multiplexers of the third block of multiplexers 20.1, ..., 20.i ..., 20.n. The first inputs of the registers of the first block of registers 9.1, ..., 9.i ..., 9.n are connected to the information inputs of the resource analyzer 6. The second inputs of the registers of the first block of registers 9.1, ..., 9.i ..., 9 .n are connected to the second output of the clock 8. The second, information inputs of the memory modules of the first memory block 10.1, ..., 10.i ..., 10.n are connected to the information inputs of the resource analyzer 6, the third inputs of the memory modules of the first memory block 10.1 , ..., 10.i ..., 10.n are connected to the third output of the clock 8. The fourth output of the clock 8 is connected to the first inputs of ISTRY second register block 12.1, ..., 12.i ..., 12.n, whose second inputs are connected to outputs of the first memory block of the memory modules 10.1, ..., 10.i ..., 10, n. The outputs of the registers of the first block of registers 9.1, ..., 9.i ..., 9.n are connected to the second, inverse inputs of the elements of the block of elements And 11.1, ..., 11.i ..., 11.n, and with the second input of the control device 16. The output of the comparison circuit 13 is connected to the second input of the second counter 15. The outputs of the second counter 15 are connected to the second inputs of the multiplexers of the first block of multiplexers 17.1, ..., 17.i ..., 17.n, control inputs which are connected to the output of the control device 16. The third input of the control device 16 is connected to the first output of the clock 8, the fourth input control system 16 is the control input 7 of the synergistic computing system. The information inputs of the multiplexers of the second block of multiplexers 18.1, ..., 18.i ..., 18.n are connected to the outputs of the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n. The outputs of the multiplexers of the second block of multiplexers 18.1, ..., 18.i ..., 18.n are connected to the second information inputs of the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n. The output of the control device 16 is connected to the third control inputs of the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n and the control inputs of the multiplexers of the third block of multiplexers 20.1, ..., 20.i ..., 20.n. The information inputs of the multiplexers of the third block of multiplexers 20.1, ..., 20.i ..., 20.n are connected to the information inputs of the resource analyzer 6, and the outputs of the multiplexers of the third block of multiplexers 20.1, ..., 20.i ..., 20 .n are the information outputs of the resource analyzer 6. The output of the control device 16 is the control output of the resource analyzer 6.

The algorithm of the SHS operation is shown in figure 4 and contains the steps of entering and analyzing the task, switching, checking for the presence of the Stop / Stop mode, analyzing the resources in the case of the Stop / Stop mode and the operation of the function blocks in the absence of the Stop / Stop mode " In the absence of the "Stop / Stop" mode, the switching of the functional blocks 1.1, ..., 1.i, ..., 1.n is not carried out and the computational process arrives according to a work program predefined by the user. In the case of the "Stop / Stop" mode, the resource analyzer, according to the algorithm shown in figure 5, performs the switching of functional blocks 1.1, ..., 1.i, ..., 1.n. SHS works as follows: first, the user analyzes the task by the criterion of connectivity (unrelated, loosely coupled, and tightly coupled task) and distributes its solution to a number of simple parallel subtasks to ensure decentralized control and reduce the length of the command word.

Accordingly, according to the results of the analysis of the initial task, the user switches the SHS resources. Such organization of the SHS operation ensures the maximum possible loading of the functional blocks 1.1, ..., 1.i, ..., 1.n of the system based on the features of the algorithm of the problem being solved and the hardware limitations on the number of functional blocks 1.1, ..., 1.i , ..., 1.n. The presence of control units 3 and command memory 4 as part of the functional blocks 1.1, ..., 1.i, ..., 1.n, as well as distributed control of the switch 2 "each with each" by means of address inputs connected to address outputs control devices 3, eliminates delays in the computing process associated with reloading the program code. The initial state of the command memory device 4, the data memory device 5.3 is entered from blocks that implement the input-output operations and is a sequence of command words and data words, respectively.

Command words in SHS have two formats (see figure 8). The first format contains an operation code field and two fields with argument addresses. The second format consists of an operation code field, an address field, an argument, and a field with the address of a command, number, or subscriber. The size of the operations code field is determined by the nomenclature of operations and must be at least] log ₂ P [binary digits, where P is the number of operations. The size of the fields with the addresses of the argument depends on the number of function blocks 1.1, ..., 1.i, ..., 1.n and must be at least] log ₂ N [each. The size of the field with the address of the command, number, or subscriber is determined by the maximum amount of addressable command or data memory, or by the number of external subscribers. The capacity of the data is determined by the specific implementation of the system, namely the requirements for the type, form and accuracy of the data presentation.

All functional blocks 1.1, ..., 1.i, ..., 1.n SHS operate in parallel and independently from each other, in accordance with the programs located in their memory devices of teams 4. Each command implements a double or single operation, which runs a certain integer number of clock cycles and, upon completion, the result is sent to switch 2 "each with each." To execute the next command, the control device 3 of the functional block 1.1, ..., 1.i, ..., 1.n selects the next command word from the command memory 4, unpacks it, generates control signals for the operating device in accordance with the operation code 5, selects from the corresponding fields the addresses of the arguments. Addresses A ₁ and A ₂ at the corresponding address outputs arrive at switch 2 "each with each."

Switch 2 "each with each" provides a direct connection of the first and second information inputs of the functional block 1.1, ..., 1.i, ..., 1.n with the outputs of the functional blocks 1.1, ..., 1.i, .. ., 1.n, the numbers of which are received by the switch 2 "each with each", respectively, at the first and second address inputs and ensures the transfer of information from the outputs of functional blocks 1.1, ..., 1.i, ..., 1.n to information entrances. The obtained information is used by the next team as arguments when the operating device 5 implements a double or single operation. The address of the command, number or subscriber selected from the format 2 commands is processed directly by the control device 3 when implementing individual control transfer commands, reading or writing a number, and also input / output commands.

Resource analyzer 6 is designed to organize recovery procedures in the SHS in the presence of the Stop / Stop mode in the operation of functional blocks 1.1, ..., 1.i, ..., 1.n. The algorithm of the resource analyzer 6 is shown in figure 5 and contains the steps:

- input of the results of the analysis of the problem. At this stage, according to the results of the analysis of the task by the user, the contents of the command memory 4 and the data memory device 5.3 from the functional blocks 1.1, ..., are entered into the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n 1.i, ..., 1.n. This stage is necessary for storing the source data of the problem being solved;

- determination of the number of the malfunctioning functional block 1.1, ..., 1.i, ..., 1.n. At this stage, with the "Stop / Stop" mode in operation of the functional blocks 1.1, ..., 1.i, ..., 1.n, the number of the faulty functional block 1.1, ..., 1.i, ... is determined , 1.n by entering into the registers of the first block of registers 9.1, ..., 9.1 ..., 9.n the contents of the flag register of the functional blocks 1.1, ..., 1.i, ..., 1.n. The logical unit signal in the HF flag indicates the presence of the Stop / Stop mode in the operation of this function block. The registers of the first block of registers 9.1, ..., 9.i ..., 9.n are entered into the registers of the flag register of the functional blocks 1.1, ..., 1.i, ..., 1.n by the first synchronizer 8 at the end of which, at the output of the registers of the first block of registers 9.1, ..., 9.i ..., 9.n, the number of the inoperative functional block is fixed. In other words, the value 0 of the HF flag indicates the presence of the Stop / Stop mode in the operation of this function block. Moreover, the register number of the first block of registers 9.1, ..., 9.i ..., 9.n uniquely corresponds to the number of the functional block 1.1, ..., 1.i, ..., 1.n. Thus, the register number of the first block of registers 9.1, ..., 9.i ..., 9.n, in which the 0 flag HF is fixed, corresponds to the number of the inoperative functional block 1.1, ..., 1.i, ..., 1.n. According to the second clock cycle of the clock 8, information from the first block of registers 1, ..., 9.i ..., 9.n is fed to the memory modules of the first block of memory 10.1, ..., 10.i ..., 10.n on recording control inputs. These signals are used to record information from functional blocks 1.1, ..., 1.i, ..., 1.n (information is the content of functional and system registers, that is, it shows the state of the computing process in the corresponding functional block 1.1,. .., 1.i, ..., 1.n at a given time) into the memory modules of the first memory block 10.1, ..., 10.i ..., 10.n.

Obviously, in the memory module of the first memory block 10.1, ..., 10.i ..., 10.n, corresponding to the inoperative functional block 1.1, ..., 1.i, ..., 1.n, information is recorded it won’t be, because at the moment the recording control input will be a signal prohibiting the recording of information;

- definition of the least busy functional block 1.1, ..., 1.i, ..., 1.n. After determining the number of the faulty function block 1.1, ..., 1.i, ..., 1.n, the least busy function block 1.1, ..., 1.i, ..., 1.n is determined to reallocate resources SHS from the inoperative functional block 1.1, ..., 1.i, ..., 1.n to the least occupied functional block 1.1, ..., 1.i, ..., 1.n. For this, the third clock cycle 8 information about the contents of the command counter of functional blocks 1.1, ..., 1.i, ..., 1.n from the memory modules of the first memory block 10.1, ..., 10.i ..., 10 .n goes to the registers of the second block of registers 12.1, ..., 12.i ..., 12.n, the comparison circuit 13, the elements of the block And 11.1, ..., 11.i ..., 11.n. Moreover, the inputs of the elements of the block And 11.1, ..., 11.i ..., 11.n, which mask the passage of information through the elements And, are inverse. This is necessary so that at the output from the block of elements And 11.1, ..., 11.i ..., 11.n receive the contents of the command counter, or in other words, the address of only an inoperative functional block in the SHS, the addresses of other functional blocks 1.1 , ..., 1.i, ..., 1.n coming from the registers of the first block of registers 9.1, ..., 9.i ..., 9.n will not go through the block of elements AND 11.1, ... , 11.i ..., 11.n. The fourth clock cycle 8 information about the address of the faulty functional block 1.1, ..., 1.i, ..., 1.n is entered in the first counter 14, and information about the addresses of the working functional blocks 1.1, ..., 1.i, ..., 1.n is entered into the comparison circuit 13. The comparison circuit 13 is a combinational logic circuit, at the output of which the contents of the instruction counter of the least occupied function block 1.1, ..., 1.i, ..., 1.n and his address in the SHS. The contents of the instruction counter of the least occupied function block 1.1, ..., 1.i, ..., 1.n are entered into the second counter 15 by the fifth clock pulse of the clock 8, and the number of the least occupied function block 1.1 is entered into the control device 16 of the resource analyzer 6 , ..., 1.i, ..., 1.n;

- reallocation of resources of an inoperative functional block 1.1, ..., 1.i, ..., 1.n to the least loaded functional block 1.1, ..., 1.i, ..., 1.n. For this, the control device 16 according to the information received from the first block of registers 9.1, ..., 9.i ..., 9.no inoperative functional block 1.1, ..., 1.i, ..., 1.n and the received information from the comparison circuit 13 about the least occupied functional block 1.1, ..., 1.i, ..., 1.n generates control words for the multiplexers of the first block of multiplexers 17.1, ..., 17.i ..., 17 .n, the second block of multiplexers 18.1, ..., 18.i ..., 18.n, the third block of multiplexers 20.1, ..., 20.i ..., 20.n and the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n of the first block of multiplexers 17.1, ..., 17.i ..., 17.n switching the contents of the first 14 and second 15 counters onto the address bus of the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n corresponding to the inoperative functional block 1.1, ..., 1.i, .. ., 1.n and the least busy function block 1.1, ..., 1.i, ..., 1.n. This action prepares for receiving information by the least busy functional block 1.1, ..., 1.i, ..., 1.n from an inoperative functional block 1.1, ..., 1.i, ..., 1.n. Then, according to the generated control word, the multiplexers of the second block of multiplexers 18.1, ..., 18.i ..., 18.n, and the multiplexers of the third block of multiplexers 20.1, ..., 20.i ..., 20.n connect the output of the module memory of the second memory block 19.1, ..., 19.i ..., 19.n corresponding to an inoperative functional block 1.1, ..., 1.i, ..., 1.n to the input of the memory module of the second memory block 19.1 , ..., 19.i ..., 19.n, corresponding to the least occupied functional block 1.1, ..., 1.i, ..., 1.n. Then, the contents of the memory module of the second memory block 19.1, ..., 19.i ..., 19.n corresponding to the inoperative functional block 1.1, ..., 1.i, ..., 1.n are written to the memory module the second memory block 19.1, ..., 19.i ..., 19.n, corresponding to the least occupied functional block 1.1, ..., 1.i, ..., 1.n. Thus, the resource analyzer redistributed the program of work of functional blocks in the memory modules of the second memory block 19.1, ..., 19.i ..., 19.n;

- re-switching (reconfiguration) of SHS resources. At this stage, according to the control word generated by the control device 16 of the resource analyzer 6, the function blocks 1.1, ..., 1.i, ..., 1.n SHS are reconnected.

The work of the resource analyzer can be considered on the example of the implementation of the formula:

Assume that the SHS consists of 6 functional blocks and all the blocks are operational, then the implementation of formula (1) occurs, as shown in figures 6.1 and 6.2. The resource analyzer 6 in this case monitors the operation of the SHS by checking for the presence of the Stop / Stop mode. When one of the functional blocks fails, the resource analyzer 6 performs restoration procedures in accordance with the above algorithm. For example, the fifth functional block of the SHS is out of order, then the implementation of formula (1) will look different, as shown in figure 7.1 and figure 7.2. As follows from the consideration of figure 7.2, the "work" of the fifth functional block takes on the fourth functional block. The work of the SHS continues, despite the failure of one of the functional blocks.

Thus, the proposed SHS while maintaining the advantages of the prototype is restored and maintains operability in case of failure of the functional blocks. Figure 9 illustrates this.

Information sources

1. The architecture of computer systems and networks: Textbook. The allowance / T.P. Baranovskaya, V.I. Loyko, M.I. Semenov, A.I. Trubilin; Ed. V.I. Loyko. - M.: Finance and Statistics, 2003. - 256 p .;

2. Golovkin B.A. Computing systems with a large number of processors. - M .: Radio and communications, 1995. - 320 p .;

3. Evreinov E.V. Homogeneous computing systems, structures, and environments. - M .: Radio and communications, 1981. - 208 p .;

4. Issues of cybernetics. Fault tolerant multi-machine and multi-processor computing systems. Ed. I.V. Prangishvili, E.M. Mammadli. - M.: Publishing House of the Academy of Sciences of the USSR, 1989. - 196 p .;

5. Shakhnovich I. This century and the future. // Electronics: Science, Technology, Business, N 6 ,: 1999, pp. 8-11;

6. Kuzminsky M. Domestic microprocessors: Elbrus 2K. // Open Systems, N 5-6, 1999, pp. 8-13;

7. Computers on VLSI. Book 1, Trans. with japan. // Motoska T., Tomita S., Tanaka X. et al. - M.: Mir, 1988, pp. 65-66, 155-158;

8. RF patent 2179333, G 06 F 15/173. Synergistic computing system / N.V. Streltsov // 06/13/2000.

Claims (2)

1. A synergistic computing system containing N function blocks, an “each with each” switch having N information inputs, 2N address inputs and 2 N information outputs, each functional block consists of a control device, a command memory device and an operating device that implements double and single operations, and also has two information inputs, two address outputs and one information output, and the first information input of the K-th functional block (K = 1, ..., N) is connected to the (2K-1) -th information output each-to-each switch house, the second information input connected to the 2K information output of the each to each switch, the first address output connected to the (2K-1) -th address switch input to the each to each, the second address output connected to the 2Kth address input of the switch "each with each", the information inputs of the functional block are the information inputs of the control device, the address outputs of the functional block are, respectively, the first and second address outputs of the control device, the third address the control device stroke is connected to the address input of the command memory device, the command input / output of the control device is connected to the command input / output of the command memory device, the control output of the control device is connected to the control input of the operating device, the first and second information outputs of the control device are connected to the first and the second information inputs of the operating device, the information output of the operating device is the information output of the functional unit a, and the operating device comprises an input / output device and / or an arithmetic logic device and / or a data memory device, the first information input of the operating device being an information input of an input / output device, an arithmetic logic device and a data memory device, the second the information input of the operating device is the address input of the input-output device and the data memory device and the second information input of the arithmetic logic device, the control input of the operational of the device is the control input of the input / output device, the arithmetic logic device and the data memory device, the information output of the input / output device, the arithmetic logic device and the data memory device is the information output of the operating device, characterized in that a resource analyzer having N information inputs and a control input, N information outputs and a control output, and (1, ..., N) the information inputs of the resource analyzer are connected respectively to the information with the outputs (1, ..., N) of the functional blocks, the information outputs (1, ..., N) of the resource analyzer are connected respectively to the information inputs (1, ..., N) of the "each with each" switch, the control output the resource analyzer is connected to the control input of the switch "each with each", and the control input of the resource analyzer is simultaneously the information input of the synergistic computing system. 2. The synergistic computing system according to claim 1, characterized in that the resource analyzer comprises a first block of registers, a second block of registers, a first block of memory, a second block of memory, a block of AND elements, a first counter, a second counter, a comparison circuit, a control device, a first a multiplexer block, a second multiplexer block, a third multiplexer block and a clock generator, wherein the information inputs of the resource analyzer are connected to the first inputs of the registers of the first block of registers, with the second information inputs of the memory modules the first memory block and with the information inputs of the multiplexers of the third block of multiplexers, the second inputs of the registers of the first block of registers are connected to the second output of the clock generator, the first output of which is connected to the clock input of the second counter, the third inputs of the memory modules of the first memory block are connected to the third output of the clock generator, the outputs of the registers of the first block of registers connected to the first inputs of the memory modules of the first memory block, with the second, which are inverse, the inputs of the elements AND the block of elements AND and with the second input of the control unit, the outputs of the memory modules of the first memory block are connected to the first inputs of the elements AND of the group of elements AND and to the second inputs of the registers of the second block of registers, the first inputs of which are connected to the fourth output of the clock generator, the outputs of the registers of the second block of registers are connected to the inputs of the comparison circuit which is connected to the second input of the second counter, the outputs of which are connected to the second inputs of the multiplexers of the first block of multiplexers, the control inputs of which are connected to the output control device, the third input of the control device is connected to the first output of the clock generator, the fourth input of the control device is the information input of the synergistic computer system, the outputs of the elements AND the block of elements And are connected to the input of the first counter, the output of which is information about the address of the faulty functional block of the synergistic computer system, arriving at the first inputs of the multiplexers of the first block of multiplexers, the first input of the control device is connected to the second the output of the comparison circuit, which generates information about the least occupied functional unit of the synergistic computing system, the information inputs of the multiplexers of the second block of multiplexers are connected to the outputs of the memory modules of the second memory block, the outputs of the multiplexers of the second block of multiplexers are connected to the second information inputs of the memory modules of the second memory block, the first information the inputs of which are connected to the outputs of the multiplexers of the first block of multiplexers, the output of the control device is It is controlled by the control output of the resource analyzer and connected to the control inputs of the memory modules of the second memory block and multiplexers of the third block of multiplexers, the outputs of which are information outputs of the resource analyzer.

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