RU2198422C2 - Asynchronous synergistic computer system - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: system that may be used for implementing algorithms admitting paralleling at command level has N functional units each incorporating choice flag shaping unit, choice flag memory, logic number register, two FIFO memory buffer units, and memory exchange, each incorporating command memory device, control device, and operating device. EFFECT: enhanced capacity of computer system. 8 cl, 4 dwg

Description

 The invention relates to computer technology and can be used in the construction of high-performance computing systems to solve problems whose algorithms allow parallelization at the command level.

 A device, microprocessor IA-64 (see. Shakhnovich I. Century present and the future. - J. Electronics: Science, Technology, Business, 1999, 6, p. 8-11), which implements parallelism at the command level using the concept of " long command word. " The device consists of a cache of instructions of the 1st level, a cache of data of the 1st level, a common cache of the 2nd and 3rd levels, a control device, a file of specialized registers: integers, floating point, branching and predicates There are four types of functional device groups: four integer arithmetic devices, two floating point operations devices, three branch devices, one data memory access device. Functional devices are managed centrally using long command words of a fixed size, each of which contains three simple commands that define the operations of three different functional devices. The sequence of simple commands in the word, as well as the relationship between words, is determined by the mask field in the word.

The disadvantages of this device are:
additional memory costs for program code caused by a fixed size of the control word;
suboptimal use of functional devices and, as a result, reduced performance due to an imbalance in the number of functional devices and the number of simple commands in a command word, specialization of functional devices and registers, mismatch in the capacity of a functional memory device (maximum one number per clock) with the capabilities of functional devices of integer operations and floating point operations.

 A device is also known, the E2K microprocessor (see Kuzminsky M. Domestic microprocessors: Elbrus 2K. - Open Systems, 1999, 5-6, p. 8-13), using the same concept of a "long command word" to implement parallelism. The device consists of a cache of instructions of the 1st level, a cache of data of the 1st level, a general cache of the 2nd level, a pre-paging buffer, a control device, a file of universal registers and a group of similar functional devices based on arithmetic -Logic devices (ALU) and combined into two clusters. The length of the command word that controls the operation of functional devices is variable.

 The disadvantages of this device include a decrease in device performance when reloading the cache of level 1 commands due to a mismatch between the speed of fetching commands and the speed of filling it, as well as the widespread use of data in the shared cache of level 2 and / or RAM.

 Also known is the device, the multiscalar microprocessor Kin (see Korneev V., Kiselev A. Modern microprocessors. M., Nolidzh, 2000, pp. 75-76), which is based on the implementation of parallelism at the level of basis blocks. In this case, the basic block is understood as a sequence of data conversion commands in registers and memory, ending with a transition command. The microprocessor consists of a set of functional blocks for various purposes: interpretation of transition instructions, interpretation of arithmetic, logical and shift instructions, execution of memory access instructions. Data exchange between function blocks is performed in asynchronous mode through FIFO queues. Each block selects elements from the input queue as they arrive, performs the specified actions, and puts the result in the output queue. With such an organization, the flow of commands is distributed between the blocks as a stream of packets containing tags and other necessary information to control the functional blocks.

 The process of fetching and decoding instructions is centralized, with the selected and decoded instructions of the next basic block being placed in the cache memory of the decoded instructions. Each team receives a unique dynamic tag when placed. After eliminating redundant WAR and WAW dependencies between teams in the rename register blocks, the teams enter the organization block for extraordinary execution.

 From the block of extraordinary execution, the commands are transferred to the backup stations, in which they expect the operands to be ready to start their execution.

 Commands with ready-made operands are sent by redundant stations for execution to function blocks, the results of which are transmitted again to the redundant stations, to the block for the extraordinary execution of commands and, in the case of transition commands, to the block for prefetching commands.

The disadvantages of this device are
complex logic of support for the extraordinary execution of commands and hardware verification of the presence of interdependencies between teams, increasing unproductive time costs and the amount of hardware support for dynamic parallelization;
the efficiency of parallelization is practically limited by the level of linear sections (base blocks), since parallelization inside the base block is performed dynamically by examining the program code at the execution stage and, therefore, does not have sufficient time resources for analysis and optimization of information links between teams;
a high level of unproductive losses caused by the greedy prefetch of teams, with an incorrect assessment of the direction of transition.

 The closest in technical essence and the achieved result to the claimed device is the electronic computer QA-2 (VLSI Computers, Book 1, Translated from Japanese. T. Motoska, S. Tomita, X. Tanaka et al. - M . World, 1988, pp. 65-66, 155-158 - prototype). This device consists of a control device, a unit of collective specialized registers, a switching network, N similar functional devices (in the described specific implementation of the prototype N = 4), built on the basis of universal arithmetic-logic devices. The switching network is implemented on the principle of "each with each", has N inputs, 2N outputs and provides a direct connection of the output of any arithmetic-logic device with the inputs of other arithmetic-logic devices.

 Device management is centralized. A long command word of a fixed size contains four fields (simple commands) for controlling arithmetic and logic devices, a field for accessing four different banks of the main memory, and a field for controlling the sequence of simple commands. Simple commands contain information about the code of the operation to be performed, the length of the operands, the address of the source registers of the left and right operands of the arithmetic logic device, and the address of the destination registers.

 The disadvantages of the known computers are as follows. A fixed length of the control word leads to non-optimal use of memory resources, namely, the field is present in the command word regardless of whether or not the corresponding arithmetic-logical device is used. A decrease in productivity is caused by the inability to directly receive data from memory by arithmetic-logic devices, since the data must be previously entered into the collective register block, as well as setting operations with different durations in one command word. In the latter case, short operations await the execution of the longest.

 The objective of the invention is to increase the performance of a computing system.

The problem is solved in that in the proposed asynchronous synergistic computer system containing N functional blocks, a "each with each" switch having N information inputs, 2N address inputs and 2N information outputs, according to the invention, each functional block consists of a control device, a memory device commands and an operating device that implements double and single operations, and also has two identification inputs of arguments, two inputs of signs of readiness of arguments, two information input inputs, identification output of arguments, two outputs of argument attributes, two address outputs, identification output of result, output of result attribute, information output, output of logical number, N inputs of signs of permission to select commands, output of sign of permission to select commands. The switch additionally contains N identification inputs of results, N inputs of signs of readiness of results, N identification inputs of arguments, 2N inputs of signs of arguments, N inputs of logical numbers, 2N identification outputs of arguments, 2N outputs of signs of readiness of arguments. The first and second identification inputs of the arguments of the kth function block (k = 1, ..., N) are connected respectively to the (2k-1) th and 2kth identification outputs of the arguments of the switch. The first and second inputs of the signs of readiness of arguments are connected respectively to the (2k-1) th and 2k-th outputs of the signs of readiness of arguments of the switch, and the first and second information inputs are connected respectively to the (2k-1) th and 2k-m information outputs of the switch . The identification output of the argument is connected to the kth identification input of the switch arguments. The first and second outputs of the attributes of the arguments are connected respectively to the (2k-1) th and 2k-th inputs of the signs of the arguments of the switch, and the first and second address outputs are connected respectively to the (2k-1) th and 2k-th address inputs of the switch. The identification output of the result is connected to the k-th identification input of the results of the switch, the output of the sign of readiness of the result is connected to the k-th input of the signs of readiness of the results of the switch, and the information output of the function block is connected to the k-th information input of the switch. The output of the sign of permission to select commands is connected to the k-th input of signs of permission to select commands of all functional blocks. Identification inputs of arguments, inputs of signs of readiness of arguments and information inputs of the function block are the corresponding inputs of the control device. The identification output of the arguments, the outputs of the arguments of the arguments and the address outputs of the function block are the corresponding outputs of the control device, the third address output of which is connected to the address input of the command memory device. The command input / output of the control device is connected to the command input / output of the command memory device, and the identification and control outputs of the control device are connected respectively to the identification and control inputs of the operating device. The first and second information outputs of the control device are connected respectively to the first and second information inputs of the operating device. The identification output of the result, the output of the result sign and the information output of the operating device are the corresponding outputs of the functional block. The output of the logical number, N inputs of signs of permission to select commands and the output of signs of permission to select commands of the functional block are the corresponding outputs and inputs of the control device. The control device consists of a command selection block, a command decryption block, an executable command generation block, a command execution control block, a command selection permission block, an information connectivity register having a dimension of N bits, memory for busy tags, readiness memory for the arguments, buffer memory of the operation code, buffer memory of the first argument and buffer memory of the second argument, having a size of L words. The address output of the command select block is the third address output of the control device, the command output of the command select block is the command output of the control device, the first identification output of the command select block is connected to the address read memory input of the busy labels. The input sign of the busy label of the command selection block is connected to the information output of the occupied label memory, the second identification output of the command selection block is connected to the identification input of the command decryption block and the address input of the busy label memory record, and the output of the busy flag of the command selection block is connected to the busy memory information input tags. The control input of the command selection block is connected to the control output of the command decryption block, the information input of the command selection block is connected to the third information output of the command execution control block, and the output of the command selection permission signal of the command block is the corresponding output of the control device. The command input of the command decryption unit is the command input of the control device, and the identification output of the arguments, the outputs of the arguments of the arguments, the address outputs of this block are the corresponding outputs of the control device. The information and control output of the command decryption unit is connected to the information and control input of the executable command generation unit, the identification inputs of the arguments, the inputs of the signs of readiness of the arguments and the information inputs of which are the corresponding inputs of the control device. The first identification output of the executable command generation unit is connected to the address input of the readiness memory of the arguments, the second, third and fourth identification outputs of the execution command generation unit are connected respectively to the address inputs of the buffer entries of the operation code, the buffer memory of the first argument and the buffer memory of the second argument. The first information input-output of the block for generating the executable command is connected to the information input-output of the memory of readiness of the arguments, the second, third and fourth information outputs of the block for generating the executable command are connected respectively to the information inputs of the buffer memory of the operation code, the buffer memory of the first argument and the buffer memory of the second argument . The output of the sign of the readiness of the command of the block forming the executable command is connected to the input of the sign of the readiness of the command of the command execution control block. The fifth identification output of the executable command generation unit is connected to the identification input of the command execution control unit, the first, second and third identification outputs of which are connected respectively to the address inputs of reading the buffer memory of the operation code, the buffer memory of the first argument and the buffer memory of the second argument, and the first, second and the third information inputs of this block are connected respectively to the information outputs of reading the buffer memory of the operation code, the buffer memory of the first argument cient buffer memory and the second argument. The output of the logical number of the command execution control unit is the corresponding output of the control device. The fourth identification output of the command execution control unit is connected to the address input of the busy mark memory record, and the output of the mark of the mark of the command control unit is connected to the information input of the busy mark memory. The output of the information connectivity installation of the command execution control unit is connected to the input of the information connectivity register. The fifth identification output of the command execution control unit is the identification output of the control device, the control output, the first and second information outputs of the command execution control unit are the corresponding outputs of the control device. The output of the information connectivity register is connected to the information connectivity input of the command selection permission block, the output of the permission flag of which is connected to the input of the permission flag of the command selection block. The N inputs of command selection enable signals of the command selection enable block are the corresponding inputs of the control device. The switch consists of N switching nodes, each of which includes N selection devices containing a logical number register with a bit capacity] log ₂ N [bits, block for the formation of selection signs, a memory of selection signs having a size of L words, two buffer blocks of FIFO memory. At all switching nodes for the kth selection device (k = 1, .... N), the kth information input of the switch is connected to the first information inputs of the buffer blocks of the FIFO memory, the kth identification input of the result is connected to the second information inputs the buffer blocks of the FIFO memory and the address input of reading the memory of the signs of choice, the k-th input of the sign of readiness of the result is connected to the signal input of reading the memory of the signs of choice. In all the selection devices of the kth switching node (k = 1, ..., N) (2k-1), the address input of the switch is connected to the address inputs of the first argument of the blocks for forming the selection signs, the 2nd address address of the switch is connected to the address the inputs of the second argument of the blocks of forming the signs of choice, the (2k-1) -th input of the signs of the arguments is connected to the inputs of the sign of the first argument of the blocks of the signs of formation, the 2nd k-input of the signs of arguments is connected to the inputs of the sign of the second argument of the blocks of forming signs, the k-th logical number input connected with the inputs of the registers of the logical number, the kth identification input of the argument is connected to the address inputs of the memory record of the selection features. For all selection devices, the output of the register of logical numbers is connected to the input of the logical number of the block for forming the signs of selection, the output of the sign of the presence of arguments of the block for forming signs of the selection is connected to the signal input of the recording memory of the signs of choice, the output of signs of the first and second arguments are connected respectively to the first and second information inputs of the memory signs of choice. The first information output of the selection characteristic memory is connected to the recording signal input of the first buffer block of the FIFO memory, the second information output of the selection characteristic memory is connected to the recording signal input of the second buffer block of the FIFO memory. All the first buffer blocks of the FIFO memory of the kth switching node are connected in series with the read signal input into the ring, and the first information outputs of the first buffer blocks of the FIFO memory are combined and are the (2k-1) -th information output of the switch. The second information outputs of the first buffer blocks of the FIFO memory are combined and are the (2k-1) -th identification output of the switch arguments, the outputs of the availability indicators of the first buffer blocks of the FIFO memory are combined and are the (2k-1) -th output of the signs of the readiness of the switch arguments. All the second buffer blocks of the FIFO memory of the kth switching node are also connected in series with the read signal input to the ring, and the first information outputs of the second buffer blocks of the FIFO memory are combined and are the 2kth information output of the switch. The second information outputs of the second buffer blocks of the FIFO memory are combined and are the 2kth identification output of the switch arguments, the outputs of the readiness indicators of the second buffer blocks of the FIFO memory are combined and are the 2kth output of the signs of the readiness of the switch arguments.

 In addition, according to the invention, depending on the conditions of its use, the operating device may comprise an input-output device and / or an arithmetic logic device and / or a data memory device, the first information input of the operating device being the information input of an input-output device, arithmetic the logical device and the data memory device, the second information input of the operating device is the address input of the input-output device and the data memory device and the second information ion-input arithmetic logic unit, the identification and control inputs of the operating unit are, respectively, the identification and the control inputs of input-output devices, an arithmetic logic unit and a data memory. The identification output of the result, the output of the result attribute and the information output of the input / output device, the arithmetic logic device and the data memory device are, respectively, the identification output of the result, the output of the result attribute and the information output of the operating device.

 Signs in the indicated relationship in the process of conducting a search for novelty were not found, are significant and, together, provide an increase in system performance. This is achieved as follows. The introduction into the composition of the asynchronous synergistic computing system of functional units that implement the input-output and write-read data, connecting them to the switch in the same way as other system units are connected, eliminates the intermediate information medium in the form of a register file and, accordingly, reduces the time access to data, as well as increase due to the redistribution of blocks within the system, the flow of data received for processing to a volume that provides the maximum possible load of functional ith blocks of the system based on the features of the algorithm of the problem being solved and hardware limitations on the number of functional blocks. Decentralization of control in an asynchronous synergistic computer system and, as a result, the inclusion of commands connected in this way into the structure of the functional blocks of the control device and the memory device, as well as the distributed control of the switch via address inputs connected to the address outputs of the control device, eliminates delays in the computing process related to reloading program code. This is achieved by the fact that in the proposed decentralized system, the length of the command word is sharply reduced. So, for a system consisting of 16 functional blocks, the length of the control word for the vast majority of operations will be 16 bits, which is several times less than the length of a simple command for the prototype. Accordingly, the need for instruction cache disappears. The required rate of receipt of the command words can be implemented, for example, by the parallel access method, providing simultaneous reading of the sequence of command words.

 Entering identification marks for commands, arguments and calculation results, buffering the transfer of information between parallel processes in the system, entering signal signs of the readiness of results, arguments and commands allow you to organize an asynchronous execution mode of commands, providing the issuance and reception of results immediately after the operation and the implementation of operations readiness arguments. Controlling the execution of commands from the data stream (by the readiness of the arguments) makes it possible to exclude the execution time of commands, as one of the parameters, when solving the parallelization task in the process of compiling programs, and also reduces the downtime of functional blocks.

 In addition, it should be noted that the unification of intra-system inter-unit communications, as well as the possibility of including various functional blocks in the system according to the set of operations being implemented, makes it possible to optimize the volume of hardware in terms of specific applications for specialized systems in terms of overall mass characteristics and power consumption. The introduction of the information connectivity register into the control device provides the possibility of organizing the parallel and independent execution of several informationally unrelated tasks, and the input of a logical number into the register registers creates the basis for the effective solution of the system reconfiguration task in the event of failure of individual functional units and the backup task.

 In FIG. 1 is a structural diagram of an asynchronous synergistic computing system; figure 2 - the main formats of the command words; figure 3 is an information graph of the formula (1) in tier-parallel form; figure 4 is an information graph of the formula (2) in tier-parallel form.

Asynchronous synergistic computing system (Fig. 1) contains functional blocks 1.1, .., 1.N, switch 2 of the type "each with each", having N information inputs i ₁ , ..., i _N , 2N address inputs a ₁ , a ₂ , ..., a _2N-1 , a _2N and 2N information outputs o ₁ , o ₂ , ..., o _2N-1 , o _2N (Fig. 1 shows the connections for the N-th functional block). Each functional block consists of a control device 3, a memory device for commands 4 and an operating device 5 that implements two-place and one-place operations, and also has two identification inputs of arguments MA ₁ and MA ₂ , two inputs of signs of readiness of arguments SA ₁ and SA ₂ , two information input I ₁ and I ₂ , the identification output of the arguments M, two outputs of the characteristics of the arguments S ₁ and S ₂ , two address outputs A ₁ and A ₂ , the identification output of the result MR, the output of the result sign SR, information output O, the output of the logical number LN, N in odov features enable selection commands sk _1, ..., sk _N, yield signs SK enable selection commands. The switch also has N identification inputs of the results mr ₁ , ..., mr _N , N inputs of the readiness signs sr ₁ , ..., sr _N , N identification inputs of the arguments m ₁ , ..., m _N , 2N inputs of the arguments s ₁ , s ₂ , ..., s _2N-1 , s _2N , N inputs of logical numbers ln ₁ , ..., ln _N , 2N identification outputs of arguments ma ₁ , ma ₂ , ..., ma _2N-1 , ma _2N , 2N outputs of signs of readiness of arguments sa ₁ , sa ₂ , ..., sa _2N-1 , sa _2N . The first and second identification inputs of the arguments MA ₁ and MA _{2 of the} k-th functional block (k = 1, ..., N) are connected respectively to the (2k-1) th and ₂ k-th identification outputs of the arguments of the switch ma _2N-1 and ma _2N , the first and second inputs of the signs of readiness of the arguments SA ₁ and SA _{2 are} connected respectively to the (2k-1) -th and 2k-th outputs of the signs of readiness of the arguments of the switch sa _2N-1 and sa _2N , the first and second information inputs I ₁ and I _{2 are} connected respectively to the (2k-1) th and 2k-th information outputs o _2N-1 and o _{2N of the} switch. The identification output of the argument M is connected to the kth identification input of the arguments of the switch m _N , the first and second outputs of the signs of arguments S ₁ and S _{2 are} connected respectively to the (2k-1) and 2k-th inputs of the signs of the arguments of the switch s _2N-1 and s _2N , the first and second address outputs A ₁ and A _{2 are} connected respectively to the (2k-1) th and 2k-th address inputs of the switch a _2N-1 and a _2N . The identification output of the result MR is connected to the k-th identification input of the results of the switch mr _N , the output of the sign of readiness of the result SR is connected to the k-th input of the signs of readiness of the results of the switch sr ₁ , the information output of the function block O is connected to the k-th information input of the switch i _N. The output of the enable command selection enable flag SK is connected to the kth input of the enable command selection enable signs sk _{N of} all functional blocks. The identification inputs of the arguments MA ₁ and MA ₂ , the inputs of the signs of readiness of the arguments SA ₁ and SA ₂ and the information inputs I ₁ and I _{2 of the} function block are the corresponding inputs of the control device 3. The identification output of the arguments M, the outputs of the signs of the arguments S ₁ and S ₂ , and and address outputs of the functional blocks a ₁ and a ₂ are the respective outputs of the control device 3, the third address output control unit 3 is connected to the address input of instruction memory 4. The command input-output control unit 3 comp nen with the command input-output of the command memory 4, the identification and control outputs of the control device 3 are connected respectively to the identification and control inputs of the operating device 5. The first and second information outputs of the control device 3 are connected respectively to the first and second information inputs of the operating device 5, identification the output of the result MR, the output of the sign of the result of SR and the information output About the operating device 5 are the corresponding outputs of the function flax block. The output of the logical number LN, N of the input signs of the permission to select the commands sk ₁ , ..., and sk _N and the output of the sign of the permission to select the SK commands of the function block are the corresponding outputs and inputs of the control device 3. The control device consists of a command selection block 3.1, a decryption block 3.2 commands, the block forming the executable command 3.3, the command execution control block 3.4, the command selection permission block 3.5, the information connectivity register 6, the memory of the occupied tags 7, the readiness memory of the arguments 8, the buffer memory of the operation code 9, buffer memory of the first argument 10, buffer memory of the second argument 11. The address output of the command selection unit 3.1 is the third address output of the control device 3, the command output of the command selection unit 3.1 is the command output of the control device 3. The first identification output of the command selection unit 3.1 is connected to the address input for reading the memory of busy tags 7, the input of the sign of busy tags of the command selection block 3.1 is connected to the information output of the memory of the busy tags 7. The second identification output of the command selection block 3.1 is connected is connected with the identification input of the command decryption unit 3.2 and the address input of the memory recording of the busy tags 7, the output of the busy sign of the tag of the command selection block 3.1 is connected to the information input of the memory of the busy tags 7. The control input of the command selection block 3.1 is connected to the control output of the command decryption 3.2 the input of the command selection block 3.1 is connected to the third information output of the command execution control block 3.4, the output of the command selection permission flag SK of the command selection block 3.1. is the output of the control device 3. The command input of the command decryption unit 3.2 is the command input of the control device 3, the identification output of the arguments of the command decryption unit 3.2 is the identification output of the arguments M of the control device 3, the output of the sign of the first argument, the first address output, the output of the sign of the second argument and the second the address output of the command decryption unit 3.2 are, respectively, the outputs S ₁ , A ₁ , S ₂ , A _{2 of} the control device 3, the information and control output of the command decryption unit 3.2 is connected to the information and control input of the block forming the executable command 3.3. The identification inputs of the arguments, the inputs of the signs of readiness of the arguments and the information inputs of the block forming the executable command 3.3 are, respectively, the inputs MA ₁ , MA ₂ , SA ₁ , SA ₂ , I ₁ , I _{2 of} the control device 3. The first identification output of the block forming the executable command 3.3 connected to the address input of the readiness memory of the arguments 8. The second, third and fourth identification outputs of the block forming the executable command 3.3 are connected respectively to the address inputs of the buffer record of the operation code 9, buffer the memory of the first argument 10 and the buffer memory of the second argument 11. The first information input-output of the block for generating the executable command 3.3 is connected to the information input-output of the readiness memory of arguments 8. The second, third, and fourth information outputs of this block are connected respectively to the information inputs of the code buffer memory record operation 9, the buffer memory of the first argument 10 and the buffer memory of the second argument 11. The output of the sign of readiness of the command of the block forming the executable command 3.3 is connected to the input iznaka readiness of the command control unit execution command 3.4. The fifth identification output of the block for generating the executable command 3.3 is connected to the identification input of the execution control block 3.4, the first, second and third identification outputs are connected respectively to the address inputs of reading the buffer memory of operation code 9, the buffer memory of the first argument 10, and the buffer memory of the second argument 11. The first , the second and third information inputs of the command execution control unit 3.4 are connected respectively to the information outputs of reading the buffer memory of the operation code 9, the buffer memory of the first argument 10 and the buffer memory of the second argument 11. The output of the logical number of the control block 3.4 is the output LN of the control device. The fourth identification output of the command execution control unit 3.4 is connected to the address input of the memory recording of the busy tags 7, the output of the tag of the busy label of the command control 3.4 is connected to the information input of the memory of the busy tags 7. The output of the information connectivity setting of the command execution control 3.4 is connected to the information register input connectivity 6. The fifth identification output of the command execution control unit 3.4 is the identification output of the control device 3. Control output the command execution control unit 3.4 is the control output of the control device 3. The first and second information outputs of the command execution control unit 3.4 are, respectively, the first and second information outputs of the control device 3. The output of the information connectivity register 6 is connected to the information connectivity input of the command selection permission block 3.5 the output of the enable flag of which is connected to the input of the enable flag of the command selection block 3.1. The N inputs of command selection enable signals of command selection enabler 3.5 are inputs sk ₁ , ..., sk _N of control device 3. Operational device 5 comprises input / output device 5.1 and / or arithmetic logic device 5.2 / or data memory device 5.3. The first information input of the operating device 5 is the information input of the input / output device 5.1, arithmetic logic device 5.2 and data memory device 5.3. The second information input of the operating device 5 is the address input of the input / output device 5.1 and the data memory device 5.3 and the second information input of the arithmetic logic device 5.2. The identification and control inputs of the operating device 5 are, respectively, the identification and control inputs of the input-output device 5.1, arithmetic logic device 5.2 and data memory device 5.3. The identification output of the result, the output of the result attribute and the information output of the input / output device 5.1, the arithmetic logic device 5.2 and the data memory device 5.3 are, respectively, the identification output of the result MR, the output of the result attribute SR and the information output O of the operating device 5. Switch 2 consists from N switching nodes 2.1, ..., 2.N each of which includes N devices of choice 2.N.1, ..., 2.NN, containing a register of logical number 12, a block for generating features of a choice of 13, a memory of features of a choice of 14 , d and the FIFO-memory 15 and the buffer unit 16. In all switching nodes for k-th 2.NN device selection, k-th information input i _N switch is connected to the first data inputs of FIFO-memory 15 and buffer blocks 16, k-th identification the input of the result mr _{N is} connected to the second information inputs of the buffer blocks of the FIFO memory 15 and 16 and the address input of the read memory of the signs of choice 14, the k-th input of the sign of readiness of the result sr _N is the signal input to read the memory of the signs of choice 14. In all devices of choice k- th switching node 2N, (2k-1) th address input to mmutatora a _2N-1 is connected with the address inputs of the first argument blocks 13 forming feature selection, 2k-th address input switch a _2N coupled to address inputs of the second argument of the blocks 13 forming selection characteristics, (2k-1) th input arguments signs s _{2N- 1 is} connected to the attribute inputs of the first argument of the attribute generation blocks 13, the 2nd k input of the argument arguments s _{2N is} connected to the attribute inputs of the second argument of the attribute formation blocks 13, the kth input of the logical number ln _{N is} connected to the inputs of the registers of the logical number 12, the kth identif munication input argument m _N connected with the address inputs of memories recording feature selection devices 14. For all selection 2.1.1, ..., 2.NN logical number output register 12 is connected to an input of the logical number generation unit 13 feature selection, feature availability output arguments unit for the formation of signs of choice 13 is connected to the signal input of the recording memory of the signs of choice 14, outputs of signs of the presence of the first and second arguments of the block for forming signs of choice 13 are connected respectively to the first and second information inputs of memory and selection signs 14. The first information output of the memory of selection signs 14 is connected to the recording signal input of the first FIFO memory block 15, the second information output of selection signs 14 is connected to the recording signal input of the second buffer FIFO block 16. All the first FIFO buffer blocks -memory 15 of the k-th switching node 2.N are connected in series with the read signal input to the ring, and the first information outputs of the first buffer blocks of the FIFO memory 15 are combined and are the (2k-1) -th information output of the switch o _2N-1 . The second information outputs of the first buffer blocks of the FIFO memory 15 are combined and are the (2k-1) th identification output _{of the} switch arguments ma _2N-1 , the outputs of the availability indicators of the first buffer blocks of the FIFO memory 15 are combined and are the (2k-1) th output signs of readiness of the arguments sa _2N-1 switch. All the second buffer blocks of the FIFO memory 16 of the kth switching node 2. N are also connected in series with the read signal input to the ring, and the first information outputs of the second buffer blocks of the FIFO memory 16 are combined and are the 2k information output of the switch o _2N . The second information outputs of the second buffer blocks of the FIFO memory 16 are combined and are the 2kth identification output of the arguments ma _{2N of the} switch, the outputs of the readiness indicators of the second buffer blocks of the FIFO memory 16 are combined and are the 2kth output of the signs of the readiness of the arguments sa _{2N of the} switch.

 A synergistic computing system operates as follows.

 The initial state of the command memory device, the data memory device is introduced from blocks that implement input-output operations, and is a sequence of command words and data words, respectively.

Command words (Fig. 2) have two main formats. The first format contains an operation code field and two fields with argument addresses. The second format consists of an operation code field, a field with the address of the argument, and a field with the address of the command, number, or subscriber. The size of the operations code field is determined by the nomenclature of operations and must be at least] log ₂ P [binary digits, where P is the number of operations. The size of the fields with the addresses of the arguments depends on the number of function blocks and must be at least] log ₂ N [each. The size of the field with the address of the command, number, or subscriber is determined by the maximum amount of addressable command or data memory, or by the number of external subscribers.

 The capacity of the data is determined by the specific implementation of the system, namely the requirements for the type, form and accuracy of the data presentation.

 The specific application conditions determine the composition of the operational devices of the functional blocks, namely the requirements for the number and speed of input / output channels, requirements for the volume of stored data and the speed of their processing. Depending on these requirements, an asynchronous synergistic computing system can have up to N input / output devices and / or up to N arithmetic logic devices and / or up to N data memory devices in total operating devices. At the same time, combining the input-output device and / or the arithmetic logic device and / or the data memory device into one operating device is performed according to the invention, and the connection of these devices can be performed by any known method.

 All functional blocks of a synergistic computing system work in parallel and independently from each other, in accordance with the programs located in their instruction memory devices. Each command implements a double or single operation, which performs a certain integer number of clock cycles, and upon completion of the execution, the result is sent to the switch.

 The execution of a command in the system involves five successive stages.

 The first is the choice of the control word, the decryption of the operation code, the formation (if necessary, depending on the operation) of the memory of the signs of selection and the formation of the blank of the command word, which includes the recording of the corresponding signs in the memory ready arguments and the buffer memory of the operation code.

 The second stage is designed to receive the results of previous operations and write them to the corresponding buffer blocks of the FIFO memory as arguments for the operations to be performed.

 The third stage provides the reading of the arguments from the FIFO memory and writing them to the buffer memory of the first or second argument.

 The fourth stage is the selection of prepared commands from the buffer memory of the operation code, the buffer memory of the first and second arguments and issuing them for execution.

 The fifth stage is the actual execution of the operation.

 The duration of each stage is variable. At the same time in each functional block at different stages of execution can be up to L teams. At the same time, only the launch of execution commands is synchronized (the first stage). All other stages are not performed synchronously, depending on the readiness of the results, arguments, commands.

The addresses of the first executable commands are set hardware or software after entering the executable commands, while the initial state of the functional blocks 1.1, ..., 1.N and switch 2 of the asynchronous synergistic system are as follows:
the memory of the occupied marks 7, the memory of the selection signs 14 and the buffer blocks of the FIFO memory 15 and 16 are reset;
signs of readiness of results SR, signs of readiness of arguments SA ₁ and SA ₂ and signs of readiness of commands are in the "not ready" state, that is, they are equal to zero;
the state of the information connectivity register 6 is zero;
the state of the flag for enabling the selection of SK commands is zero, which corresponds to the "allowed"flag;
the state of the register of logical number 12, the readiness memory of the arguments 8, the buffer memory of the operation code 9, the buffer memory of the first argument 10 and the buffer memory of the second argument 11 is arbitrary.

 To identify commands, arguments and calculation results in an asynchronous synergistic computer system, identification marks are generated in the command selection blocks 3.1, the initial state of which is zero.

 The selection of the next command by the command selection block 3.1 starts with checking the permission flag coming from the command selection permission block 3.5. If the permission flag is equal to one ("forbidden"), then the command selection block 3.1 will be in the standby state until the value of the flag becomes zero ("allowed"), after which the command selection block 3.1 checks the identification tag is busy. To do this, the command selection unit 3.1 reads from the memory of the occupied tags 7 a word located at an address whose value is equal to the value of the identification tag. If the content of this word is zero (the tag is free tag), the command fetch unit 3.1 issues the command address to the command memory 4, writes a non-zero word to the memory of the busy tags 7 at the identifying tag value (the tag is busy) and gives the label value to the command decryption block 3.2 on the second identification output. If during reading the contents of the word are non-zero (the tag is busy indicator), the command selection block generates a flag for allowing the selection of SK commands to one and switches to the standby state until the label is released, after which the flag for enabling the selection of SK commands is set to zero , and the process of selecting commands begins anew with checking the sign of permission.

 After issuing the command address to the command memory 4, recording the tag’s busy indicator and issuing the tag value to the command decryption block 3.2, the command selection block 3.1 generates a new command address value and a new identification tag value by adding one to the old values, while adding up when calculating the new label value is carried out modulo L.

The command decryption unit 3.2 receives the command word from the command memory 4, unpacks it and analyzes the operation code. If this command requires one or two arguments from switch 2, then the command decryption unit 3.2 generates and transfers to switch 2, respectively, the value of the identification label at the output M, one or two sign values of the arguments S ₁ and S _2, and one or two the values of addresses A ₁ and A ₂ . The value of the identification tag is taken from the command selection block 3.1, the address values are taken from the command word, and the attribute values of the arguments are generated as follows: if the command uses any argument, then the value of the corresponding attribute is equal to one ("argument is used"), otherwise, the value is zero ("argument not used"). If, to execute a command, it is required to select another command word (format 2) as the data address (commands, external device) from the command memory 4, then this information is sent to the command selection block 3.1 via the control input. In this case, the command selection block 3.1 organizes the reading of the additional command word, while the identification tag does not change, and for the time of reading, a sign of permission to select SK commands equal to one is generated, that is, the choice of command words for other function blocks is prohibited.

The identification tag, operation code and address of the data (command, external device) are transmitted via the information-control output to the block for generating the executable command 5.3. Using the value of the identification tag as an address, the block for generating the executable command 5.3 resets the corresponding word of the readiness memory of arguments 8, writes the received operation code to the buffer memory of the operation code 9 and, if necessary, the data address (commands, external device) into the buffer memory of the second argument 11, and in memory of the readiness of arguments 8 - a sign of readiness of the second argument. The values of the arguments coming from other function blocks are recorded when signs of readiness of arguments SA ₁ and SA ₂ equal to one (“argument ready”) are received. In this case, the values of the identification marks received at the inputs MA ₁ and MA ₂ are used, respectively, as the addresses for writing the values of the arguments I ₁ and I ₂ to the buffer memory of the first argument 10 and the buffer memory of the second argument 11. Since the system is asynchronous, argument values may not arrive at the same time. In parallel with the recording of the values of the arguments in the memory of the readiness of the arguments 8 signs of readiness of the arguments are entered. Record of signs is as follows. At the address, the value of which is determined by the value of the identification label, the word is read from the memory of the readiness of the arguments 8. In the corresponding bits of this word, the sign of the readiness of the first or second argument (non-zero bits) is entered, after which a check is made for the availability of the two arguments. The generated word is written back to the readiness memory of arguments 8, in this case, if during the verification it is determined that both arguments are ready, a sign of the readiness of the command is formed, the value of the identification mark equal to the value of the last recorded argument, and this data is the output of the sign of the readiness of the command and the fifth the identification output is transferred to the control unit by execution of command 3.4. This block reads at the address equal to the value of the identification tag, the operation code from the buffer memory of the operation code 9, the value of the first argument from the buffer memory of the first argument 10 and the value of the second argument from the buffer memory of the second argument 11. Writes at the same address in the memory of the busy labels 7 a sign of busy label equal to zero ("label free"), and analyzes the operation code. If the incoming command does not require the use of a data memory device 5.3, arithmetic logic device 5.2, or input-output device 5.1, that is, if it does not generate a result coming to switch 2, then this command execution unit 3.4 executes this command. In particular, these are commands for generating a logical number, transferring control, loading a memory device for commands 4, forming an information connectivity register 6. Otherwise, the command execution control block 3.4 generates a new identification mark value, adding up the value obtained with unity modulo L and transmits a new identification value labels, the value of the operation code and the values of the first and second arguments to the operating device 5 according to the fifth identification output, control output and the first and second info mation outputs, respectively.

 The operating device 5 executes the command and generates a sign of readiness of the result SR, the identification mark of the result (identification output of the result MR) and the result itself (information output O).

 If the commands do not use common devices, then their parallel execution is possible, while if the result is generated on the same clock cycle, then it arrives at switch 2 in the order of execution commands.

The information connectivity register 6 has N digits and contains information about which functional blocks should select command words synchronously. The information-related functional blocks are marked with a unit in the corresponding category, namely, the k-th functional block in the k-th category. The contents of the information connectivity register 6 is used when generating a permission flag coming from the command selection permission block 3.5 to the command selection block 3.1. If at least one i-th digit of the information connectivity register 6 is equal to one and equal to sk _i , then the permission flag is equal to one ("forbidden").

 The switch is involved in the second and third stages of command execution.

For the implementation of the second stage, the memory of the signs of choice 14 is pre-formed. The formation of this memory is as follows. The block of formation of signs of choice 13 analyzes the state of signs of arguments s _2N-1 and s _2N . If the sign of the first argument s _2N-1 is equal to one, then the values of the register of logical number 12 and the address value of the first argument and a _{2N-1 are} compared. If they are equal, then the sign of the presence of the first argument is formed, which is equal to one ("the argument is"), otherwise the value of this sign is set to zero ("no argument"). Similarly, a sign of the presence of the second argument is formed. If at least one of these signs is not equal to zero, then a generalizing sign of the presence of arguments is formed, which is equal to one ("there are arguments"), otherwise its value is set equal to zero ("there are no arguments"). Further, if the sign of the presence of arguments is nonzero, then in the memory of the signs of choice 14, a two-bit word is written at the address equal to the value of the identification label received at the identification input of the argument m _N , the value of the digits of which corresponds to the values of the signs of the presence of the first and second arguments.

The result of the next operation entering the switch 2 via the information input i _{N is} accompanied by a sign of readiness of the result sr _N and an identification mark mr _N. In the selection devices 2.1.N, 2.2.N, ..., 2.NN, corresponding to this information input, from the memory of the selection signs 14 to the address, the value of which is set by the identification mark, the non-zero sign of the result being ready ("the result is ready") is performed reading the corresponding word while zeroing its contents in the memory of the selection signs 14. The first bit (first information output) of the selected word is used as a write signal to the first buffer block of the FIFO memory 15. The second bit is used as a write signal to the second uferny FIFO-memory unit 16. If the recording signal is different from zero, the corresponding FIFO-buffer memory block will be recorded the result, incoming on data input i _N and identification tags received by the ID input mr _N.

 In parallel with the process of writing to the buffer blocks of FIFO memory 15 and 16, previously recorded information is read from these blocks and transmitted to form command words. The reading process is organized cyclically, separately for all the first buffer blocks of the FIFO memory 15 of the switching node 2.N and separately for all the second buffer blocks of the FIFO memory of the same node. The read signal is transmitted in a ring from the first buffer block of the FIFO memory 15 of the device of choice 2.NN to the first buffer block of the FIFO memory of the device of choice 2.NN-1 and so on to the device of choice 2.N.1, the read signal from which is connected with the first buffer block FIFO-memory 15 of the device selection 2.NN

The next first buffer block of FIFO memory, having received a read signal, if it does not have previously recorded information, transmits this signal to the next block. If there is information, then it forms a sign of the readiness of the argument sa _2N-1 , selects the values of the result and the identification label and issues them to the information output o _2N-1 and to the identification output of the argument ma _2N-1 , respectively. The selection and delivery of information continues until all the information in this block is selected, after which a read signal is generated for the next block, etc.

Информационные графы, описывающие последовательность выполнения операций в формулах и их параллелизм, представлены в виде ярусно-параллельных форм на фиг.3 и 4.Consider the work of an asynchronous synergistic computing system, using two formulas as an example

Information graphs describing the sequence of operations in the formulas and their parallelism are presented in the form of tiered-parallel forms in figure 3 and 4.

 For definiteness, we assume that an asynchronous synergistic computing system has 16 functional blocks. Of these, 15 blocks with numbers 1 to 15 have a data memory device and an arithmetic-logical device as part of the operating device. Block 16 is an I / O block.

 Data memory devices implement read (th) and write (zp) commands of format 2 and have a duration of one clock cycle. A read command is a one-place operation that selects a number from the data memory at the address specified in the command word. The write command implements a two-place operation, the first argument of which is the number coming from the switch, and the second is the address at which the given number is written to the data memory specified in the command word.

 Arithmetic-logic devices implement the following commands: addition (+) and subtraction (-), 1 cycle long; multiplication (•), duration 2 cycles; division (/), lasting 4 steps. All commands of the computing unit have the first format, implement double-place operations, and the subtracted and divisible are specified in the first address.

 To ensure coordinated interaction of blocks, when there is a need to delay the result of execution at the output of a functional block, the "waste" (t) command of the first format is used, which saves the state of the block 1 clock cycle. You can also save the result by one clock by organizing a record in the working cell of the data memory. The recorded number at the end of the operation is not only entered into the data memory, but also goes to the output of the function block.

 We will take the following form of writing command words (see table. A).

 where <nemocop> is the symbol of the operation code; <number> - a number from 1 to 16, indicating the number of the function block, the results of which are used as an argument when performing the operation; <name> - the name of the argument whose address (after broadcasting and downloading programs) will be generated in the address field of the number.

We place the elements of the matrix (a ₁₁ , a ₁₂ , a ₁₃ , a ₂₁ , a ₂₂ , a ₂₃ , a ₃₁ a ₃₂ , a ₃₃ ) element-wise in the data storage devices of function blocks 1-9. The vectors (b ₁ , b ₂ , b ₃ ) and (c ₁ , c ₂ , c ₃ ) are element-wise in the data storage devices of functional blocks 10-12. We place the variables e, d, x in the data memory of 10, 11, 12 function blocks, the variables y and v at 13, and the variables z and w in 14 blocks.

When programming to save intermediate results for one clock cycle, we introduce an additional operand, namely the working cell r ₁ in the 14 function block.

 The results of programming the function blocks when calculating formulas (1) and (2) are presented in table 1.

 The last row of the table shows the number of commands executed by each function block when calculating these formulas.

 When programming an asynchronous synergistic computing system, it is believed that all instructions are executed in a single clock cycle. The actual duration of command execution is taken into account during the operation of the system. Table 2 presents the actual time diagram of the system.

Claims (8)

1. An asynchronous synergistic computing system containing N functional blocks, an "each with each" switch having N information inputs, 2N address inputs and 2N information outputs, characterized in that each functional block consists of a control device, an instruction memory device and an operating device which implements double and single operations, and also has two identification inputs of arguments, two inputs of signs of readiness of arguments, two information inputs, identification output of arguments, two outputs of the arguments of the arguments, two address outputs, the identification output of the result, the output of the output of the result, the information output, the output of the logical number, N inputs of signs of permission to select commands, the output of signs of permission to select commands, and N identification inputs of results, N inputs of readiness signs are entered into the switch results, N identification inputs of arguments, 2N inputs of signs of arguments, N inputs of logical numbers, 2N identification outputs of arguments, 2N outputs of signs of readiness of arguments, etc. than in the k-th functional block (k = 1, ..., N) the first and second identification inputs of the arguments are connected, respectively, with the (2k-1) -th and 2k-th identification outputs of the switch arguments, the first and second sign inputs the readiness of the arguments are connected, respectively, with the (2k-1) -th and 2k-th outputs of the signs of readiness of the arguments of the switch, the first and second information inputs are connected, respectively, with the (2k-1) -th and 2k-m information outputs of the switch, identification the argument output is connected to the kth identification input of the arguments pa, the first and second outputs of the signs of the arguments are connected, respectively, with the (2k-1) -th and 2k-m inputs of the signs of the arguments of the switch, the first and second address outputs are connected, respectively, with the (2k-1) -m and 2k-m address inputs of the switch, the identification output of the result is connected to the k-th identification input of the result of the switch, the output of the sign of readiness of the result is connected to the k-th input of the sign of readiness of the result of the switch, the information output is connected to the k-th information input of the switch, the output of the sign of selection permission to the mand is connected to the kth input of signs of allowing the selection of commands of all functional blocks, in addition, the identification inputs of the arguments, the inputs of the signs of readiness of the arguments and the information inputs of the functional block are the corresponding inputs of the control device, the identification output of the arguments, the outputs of the signs of the arguments and address outputs of the functional block are corresponding outputs of the control device, the third address output of the control device is connected to the address input of the memory device com nd, the command input-output of the control device is connected to the command input-output of the command memory device, the identification and control outputs of the control device are connected, respectively, with the identification and control inputs of the operating device, the first and second information outputs of the control device are connected, respectively, with the first and the second information inputs of the operating device, the identification output of the result, the output of the sign of the result and the information output of the operating device are the corresponding outputs of the functional block, the output of the logical number, N inputs of signs of permission to select commands of the function and the output of the sign of permission to select commands of the functional block are the corresponding outputs and inputs of the control device, the control device consisting of a block for selecting commands, a block for decrypting commands, a block for generating an executable command, a command execution control unit, a command selection permission block, an information connectivity register having a dimension of N bits, memory occupied m etc, the readiness memory of the arguments, the buffer memory of the operation code, the buffer memory of the first argument, the buffer memory of the second argument, having a size of L words, and the address output of the command selection block is the third address output of the control device, the command output of the command selection block is the command output of the control device, the first identification output of the command selection block is connected to the address input of reading the memory of the occupied tags, the input of the sign of busy tags of the command selection block is connected to the information output of the memory taken labels, the second identification output of the command selection block is connected to the identification input of the command decryption block and the address input of the memory of the occupied tags memory, the output of the tag indication of the busy block of the command selection is connected to the information input of the occupied tags memory, the control input of the command selection block is connected to the control output of the decryption block commands, the information input of the command selection block is connected to the third information output of the command execution control block, the output of the sign of permission to select the block commands The command selection is the corresponding output of the control device, the command input of the command decryption unit is the command input of the control device, the identification output of the arguments, the outputs of the arguments of the arguments, the address outputs of the command decryption unit are the corresponding outputs of the control device, the information and control output of the command decryption unit is connected to the information and control the input of the block forming the executable command, identification inputs of arguments, inputs of signs of readiness of arguments comrade and information inputs of which are the corresponding inputs of the control device, the first identification output of the executable command generation unit is connected to the address input of the readiness memory of the arguments, the second, third and fourth identification outputs of the executable instruction formation unit are connected, respectively, to the address inputs of the operation code buffer memory record, buffer memory of the first argument and buffer memory of the second argument, the first information input-output of the block forming the executable of the command is connected to the information input-output of the memory of the readiness of the arguments, the second, third and fourth information outputs of the block for generating the executable command are connected, respectively, to the information inputs of the buffer memory of the operation code, the buffer memory of the first argument and the buffer memory of the second argument, the output of the sign of readiness of the block command the formation of the executable command is connected to the input sign of the readiness of the command of the command execution control unit, the fifth identification output of the formation unit and the executed command is connected to the identification input of the command execution control unit, the first, second and third identification outputs of which are connected, respectively, to the address inputs of reading the buffer memory of the operation code, the buffer memory of the first argument and the buffer memory of the second argument, the first, second and third information inputs of the block execution control commands are connected, respectively, with the information outputs of reading the buffer memory of the operation code, the buffer memory of the first argument and the buffer memory of the second of the first argument, the output of the logical number of the command execution control unit is the output of the control device, the fourth identification output of the command execution control unit is connected to the address input of the busy label memory record, the output of the tag sign of the control unit of the command execution is connected to the information input of the busy label memory, the information setting output the connectivity of the command execution control unit is connected to the input of the information connectivity register, the fifth identification output of the control unit The execution of commands is the identification output of the control device, the control output, the first and second information outputs of the control unit of the command execution are the corresponding outputs of the control device, the output of the information connectivity register is connected to the information connectivity input of the command selection permission block, the output of which permission sign is connected to the permission sign input a command selection block, N inputs of command selection permission signs of a command selection permission block are respectively there are control device inputs, and the switch consists of N switching nodes, each of which includes N selection devices containing a logical number register with dimension] Iog ₂ N [bits, block of the formation of selection signs, a memory of selection signs having a size of L words, two buffer blocks of FIFO memory, and at all switching nodes for the k-th selection device (k = 1, ..., N), the k-th information input of the switch is connected to the first information inputs of the buffer blocks of FIFO memory, the k-th identification the input of the result is connected to by the second information inputs of the buffer blocks of the FIFO memory and the address input of reading the memory of the signs of choice, the kth input of the sign of readiness of the result is connected to the signal input of reading the memory of the signs of choice, and in all devices of the choice of the k-th switching node (k = 1, ... , N) (2k-1) -th address input of the switch is connected to the address inputs of the first argument of the blocks of formation of signs of choice, 2k-address address of the switch is connected to the address inputs of the second argument of the blocks of forming signs of choice, (2k-1) -th input of signs arguments connected to by the attribute inputs of the first argument of the attribute generation blocks, the 2nd k input of the argument attributes is connected to the attribute inputs of the second argument of the attribute formation blocks, the kth logical number input is connected to the inputs of the logical number registers, the kth argument identification input is connected to the address inputs of the characteristic memory record selection, as well as in all selection devices, the output of the register of the logical number is connected to the input of the logical number of the block forming the signs of the choice, the output of the sign of the presence of arguments of the block of the form of the selection signs is connected to the signal input of the recording of the memory of the signs of the selection, the outputs of the signs of the first and second arguments are connected, respectively, with the first and second information inputs of the memory of the signs of the selection, the first information output of the memory of the signs of the selection is connected to the signal input of the recording of the first buffer block of the FIFO memory, the second information output of the memory of the selection signs is connected to the signal input of the recording of the second buffer block of the FIFO memory, in addition, all the first buffer blocks of the FIFO memory of the k-th switching node are connected in series by the read signal input to the ring, and the first information outputs of the first FIFO memory buffer units are combined and are the (2k-1) -th information output of the switch, the second information outputs of the first FIFO memory buffer units are combined and are (2k-1) - m is the identification output of the switch arguments, the outputs of the availability indicators of the first buffer blocks of the FIFO memory are combined and are the (2k-1) -th output of the signs of readiness of the arguments of the switch, all the second buffer blocks of the FIFO memory of the k-th switching node are also connected they are sequentially a read-in signal ring in the ring, the first information outputs of the second buffer blocks of the FIFO memory are combined and are the 2kth information output of the switch, the second information outputs of the second buffer blocks of the FIFO memory are combined and are the 2kth identification output of the switch arguments, symptom outputs the readiness of the second buffer blocks of the FIFO memory are combined and are the 2k-th output of the signs of readiness of the switch arguments.  2. The system according to claim 1, characterized in that the operating device comprises an input-output device, the first information input of the operating device being the information input of the input-output device, the second information input of the operating device is the address input of the input-output device, identification and control the inputs of the operating device are, respectively, the identification and control inputs of the input-output device, the identification output of the result, the output of the result sign, and The information output of the input-output device is, respectively, the identification output of the result, the output of the result sign and the information output of the operating device.  3. The system according to claim 1, characterized in that the operating device comprises an arithmetic logic device, wherein the first information input of the operating device is the information input of the arithmetic logic device, the second information input of the operating device is the second information input of the arithmetic logic device, identification and the control inputs of the operating device are, respectively, the identification and control inputs of the arithmetic logic device, identification The output of the result, the output of the result attribute and the information output of the arithmetic logic device are, respectively, the identification output of the result, the output of the result attribute and the information output of the operating device.  4. The system according to claim 1, characterized in that the operating device comprises a data memory device, the first information input of the operating device being the information input of the data memory device, the second information input of the operating device is the address input of the data memory device, identification and control inputs of the operating device are, respectively, the identification and control inputs of the data memory device, the identification output of the result, the output of the sign result and information output of the data memory device are respectively output an identification result of feature information and output the result output of the operational device.  5. The system according to claim 1, characterized in that the operating device comprises an input-output device and an arithmetic-logic device, the first information input of the operating device being the information input of an input-output device and an arithmetic-logical device, the second information input of the operating device is the address input of the input-output device and the second information input of the arithmetic logic device, the identification and control inputs of the operating device are, respectively Namely, the identification and control inputs of the input-output device and the arithmetic-logical device, the identification output of the result, the output of the result indicator and the information output of the input-output device and the arithmetic-logical device are, respectively, the identification output of the result, the output of the result indicator and the information output of the operating room. devices.  6. The system according to claim 1, characterized in that the operating device comprises an input / output device and an arithmetic logic device and a data memory device, the first information input of the operating device being an information input of an input / output device, an arithmetic logic device and a memory device data, the second information input of the operating device is the address input of the input-output device and the data memory device and the second information input of the arithmetic logic device, is the typification and control inputs of the operating device are, respectively, the identification and control inputs of the input-output device, the arithmetic logic device and the data memory device, the identification output of the result, the output of the result attribute and the information output of the input-output device, the arithmetic-logical device and the memory device data are, respectively, the identification output of the result, the output of the sign of the result and the information output of the operating device.  7. The system according to claim 1, characterized in that the operating device comprises an input / output device and a data memory device, wherein the first information input of the operating device is an information input of an input / output device and a data memory device, the second information input of the operating device is an address input input-output devices and data memory devices, the identification and control inputs of the operating device are, respectively, the identification and control inputs of the devices and input-output data memory, an identification result output, and output the result of feature information output of input-output devices and data storage devices are respectively output an identification result of feature information and output the result output of the operational device.  8. The system according to claim 1, characterized in that the operating device comprises an arithmetic logic device and a data memory device, wherein the first information input of the operating device is an information input of an arithmetic logic device and a data memory device, the second information input of the operating device is an address input data memory devices and the second information input of the arithmetic logic device, the identification and control inputs of the operating device are, respectively Actually, the identification and control inputs of the arithmetic-logical device and the data memory device, the identification output of the result, the output of the result indicator and the information output of the arithmetic-logical device and the data memory device are, respectively, the identification output of the result, the output of the result indicator and the information output of the operating device.

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