SU1591037A1

SU1591037A1 - Arithmetic device for fast fourier transform

Info

Publication number: SU1591037A1
Application number: SU884393790A
Authority: SU
Inventors: Vladimir A Luzhetskij; Petr V Kozlyuk; Yurij N Bochkov
Original assignee: Sp Kt B Modul Vinnitskogo Polt
Priority date: 1988-03-17
Filing date: 1988-03-17
Publication date: 1990-09-07

Description

The invention relates to computing technology and is intended to build signal processing devices operating in real time. The purpose of the invention is to simplify the device. For this, the device contains multipliers 1, 2, switches 3–6, adders 7–9, subtractors U – 12 and blocks 13,14 of the shift, 4 Il.

1

OZ

m

3

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The invention relates to computing and. Designed to build signal processing devices that operate in real time

The purpose of the invention is to simplify the device.

The device performs the basic operations of the fast Fourier transform algorithm

^p - in ¹ * £ ⁱⁿ < ^{) x} ' ^(,)

where is the vector

coefficients, Fourier transforms of the input data vector - Χ = (Χ _ί ', X ,,.

XN -. dimension of transformation; η = Ιοβ ^;

(2) ^t to = (3) θκ = (four) where i - unit matrix; N - matrix of discrete Fourier rolls of dimension & two; . ·· - the symbol of the Kronker production matrix management; T - transpose symbol • 9 1.4 ϋ, κ! I ₂ p-to-1 M „.k = 8 _{? Η} -1-ι five where ϋ * - diagonal matrix,

holding real coefficients;

Р - matrix of ideal statement;

8 · - quasidiagonal matrix of the form

h 00 o o ots *

h * h 9 "o o 09

[heh

Oh h * oh oh ooo oo ·

• o o

• · about '

Oh oh oh .. what '

About About About »about about 4 * 9

where * is the sign of complex conjugation.

Matrix 8 is a cyclic shift matrix. Toe _0, each successive column can be obtained from the previous one by cyclically shifting its elements. The element of the matrix can be represented by the expression !.

9 - ί + (5)

where o (is a real number equal to the base of the system used;

3 = 1-1.

Obviously, the choice of </ equal to the base of the used number system will allow you to calculate the product of some vector X by the matrix 8 without multiplication operations. At the same time, the elements of the resulting vector. represented by the ratio

Υ I = × X, · + h * x <s-1>gaVr; ϊ = 0.1, ···· Р P (6)

where> pyu (1p - means coercion modulo p;

p is the dimension of the matrix 8.

Consider the algorithm of fast Fourier transform in accordance with the expression (1) „

Here, for the first 1οβ _2-1 iterations, a sequence of basic operations is performed in accordance with expression (6), which can be written in the opened form as follows:

Ke Υ; = Ke B; + Ке С ₍ - <Д1га В; - 1га С.);

1t Υ, · = V (Ke B, - Ke С _{ ) +

+ 1t B, + I o C ₎ . ,

where B-, C, - source operands;

Ke ^ 1t - real and respectively imaginary parts, numbers ;,

At the last Ιοβ ^ Ν iterations, a sequence of basic

operations! following from relations (2) and (3) о These basic operations have the structure of calculation, ana5 159

the logical structure of the butterfly calculation in the “classical” fast Fourier transform algorithm, and analytically can be represented as:

Г А; - "! * С; 0,

where A., A. ₊ , - the results of the calculation

basic operation;

ά. - real element

Ί

diagonal matrix ϋ »

The ratio (8) can be written in the form:

(Re = Re A. B + Re S. _ό;;

1st A; = 1t V. + 1ga C _; y μ ·

Ke A _5i = Ke. V. - Ke S. ά ,; _(e)

1t A = 1t V - 1t C. · 8 ..

I τ 1 1 I |

Figure 1 shows the block diagram of the device; FIGS. 2 and 3 of the basic operation structure by formulas (9), (7); figure 4 is a graph of the algorithm of the fast Fourier transform with N = 8 (where (o) is the basic operation

first type, O - basic operation of the first type).

The device (Fig, 1) contains the first 1 and second 2. multipliers from the first to the fourth switches 3-6, the first, second and third adders 7.8 and 9 ,. the first, second and third subtracters 10,11 and 12, the first and second blocks 13 and 14 of the shift, the inputs 15 and 16 of the real parts of the first and second operands, the input 17 of the coefficient, the inputs 18 and 19 of the imaginary parts

• respectively, the second and first operands, input 20 specifies the type of device operation, outputs 21-24,

Blocks 13 and 14 of the shift carry out the multiplication of operands on o ("When

'Processing data represented by a serial code, the shift blocks can be implemented as shift registers, and in the case of processing data represented by a parallel code, these blocks can be the wiring connections of the 3rd input bit with the th output block.

The device (Fig „1) works as follows.

In accordance with the calculation graph of the fast Fourier transform algorithm (FIG _. 4), a sequence of basic operations is first performed, defined by relation (7) (FIG. 3). Initialization of the execution of this basic operation in an arithmetic unit is carried out by applying the signal of the level "ΠοΓοΙ" to the input 20 of the device. This signal goes to the control inputs from the first, second, third and fourth switches 3,4,5 and 6, which puts them in the feed mode data from one information input to output,

The inputs 15 and 18 of the device each time the basic operation is performed (FIG. 3), respectively, are the real and imaginary parts of the first operand B, relations (7), and the real and imaginary parts of the second operand C arrive at the inputs 16 and 19 of the device relations (7)., In this case, the real and imaginary parts of the second SL operand from inputs 10 and 19 of the device through the first information inputs of the first 3 and second 4 switches, respectively, arrive at the inputs of the first 7 and second 8 adders, as well as at the inputs of the first and tue One of the subtractors 10 and 11. At the same time, the inputs of the first adder 7 and the first subtractor 10 are fed the value of the real part of the first operand B. from the gate 15 of the device. This will provide a calculation of the sum and difference of the real parts of the first and second operands B. and C _; in accordance with the basic operation (FIG. 3) ₀

Similarly, the arrival at the inputs of the second adder 8 and the second subtractor 11 of the value of the imaginary part of the first operand B. provides the calculation of the sum and difference of the imaginary parts. the first and second operands V. and S., the values of which are formed at the outputs of the second adder 8 and the second subtracter, respectively 11.

The final results of the calculation for the basic operation (7) are formed at the outputs of the third adder 9 and the third subtracter 12, for one input of which the value is applied

7

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the sums of the real parts of the first and second operands B. and C, ·, and to another input of the subtractor 12, the value of the difference of the imaginary parts of the first and second operands В _{ and С, multiplied by о / in the second block 14 of the shift, is supplied, which provides the calculation the real part of the output operand Υ. in accordance with the structure of the basic operation (fig.Z) "

Formation of the minimum part of the output Υ. is carried out at the output of the third adder 9, to one input of which the value of the difference between the real parts of the first and second operands V. and C \, multiplied in the first shift block by a constant c /, and the other input of the third adder 9 arrives. parts of the first and second operands B,. and C. from the output of the second adder 8.

The value of the real and imaginary parts of the output operand from the outputs of the third subtractor 12 and the third adder 9 through the information inputs of the fourth and third switches 6 and 5, respectively, to the outputs 24 and 22 of the device "In this mode of operation of the arithmetic device, the outputs 21 and 23 of the device, and the input 17 of the coefficient are inactive "

After performing the required number of basic operations (FIG. 3) in accordance with the graph shown in FIG. 4, the arithmetic unit is switched to the basic operations mode (FIG. "2),

Translation arithmetic device in the mode of performing the basic operation (figure 2) is carried out by applying to the input 20 of the device signal level "Log.O" ₀ This signal is fed to the control inputs * of the first, second, third and fourth switches 3,4,5 and 6 and puts them into data transfer mode of other information inputs to outputs.

During the next execution of the basic operation (FIG. 2), the inputs 15 and 18 of the device are supplied with the values of the real and imaginary parts of the first operand B., respectively, and the values of the real and imaginary parts of the second operand C, are entered at the inputs 16 and 19 of the device. At the same time, the input of the coefficient 17 of the device enters the value of the coefficient P. ·, which goes to these inputs of the first and second multipliers 1 and 2, and the other inputs of the first and second multipliers 1 and 2 from the inputs 16 and 19 of the device are applied to the real and imaginary parts of the first operand V. devices. ”After the multiplication time at the outputs of the first and second multipliers 1 and 2, the real and imaginary parts of the result of the product of the second operand C. are formed by a constant. The value of the real part of the resultant of the product from the output of the first multiplier 1 is fed to the information input of the first switch and then to the outputs of the first adder 7 and the first subtractor 10, to the other inputs from the device input 15 the value of the real part of the first operand V is given. the outputs of the first adder and the first subtractor to form the result of calculating the real parts of the first and second operands A. and A of the basic operation (Fig ₀ 2).

Similarly, the value of the imaginary part of the result of the product of the second operand C ₍ the constant H comes from the output of the second multiplier to the information input of the second switch 4, and then to one input of the second adder 8 and the second subtractor 1I, the other inputs of which receive the value of the imaginary part of the first operand In ₍ p. Device input, which will allow to calculate the values of imaginary parts of the first and second output operands A. and A. ₊₁ (Fig »2)„

C. The outputs of the first and second adders 7 and 8 of the real imaginary part of the first operand A. arrive at the outputs 21 and 22 of the device, and the real and imaginary parts of the second operand A _{; +1} arrive at the outputs 23 and 24 of the device through the information inputs of the switches 5 and 6 outputs respectively subtractors 10 and 1 1 "

Claims

Claim

An arithmetic unit for the fast Fourier transform processor containing the first and second multipliers, the first and second switches ,. the first, second and third subtractors, the input of the real part of per1591037 ω

device’s first operand is connected to the first inputs of the first adder and first subtractor, the second inputs of which are connected to the output of the first switch, the first information input of which is connected to the first input of the first multiplier and the input of the real part of the second operand the second inputs of the first and second multipliers, the first input of the second multiplier is connected to the input of the imaginary part of the second operand of the device and the first information input of the second switch, you Which is connected to the first inputs of the Second adder and the second subtractor, the second inputs of which are connected to the input of the imaginary part of the first 20 operands of the device, the first and second outputs of the device are the outputs of the first and second adders, respectively; , it contains the first and second blocks of shift, the third and fourth switches, the outputs of which are respectively the third and fourth

device outputs ^ input of operation type of which is connected to control inputs of the first, third and fourth switches, the first information input of the fourth switch is connected to the output of the second subtractor and the input of the second shift unit, the output of which is connected to the first input of the third subtractor, the output of which is connected to the second information the input of the fourth switch, the second input of the third subtractor is connected to the output of the first adder, the output of the first subtractor is connected to the input of the first shift unit and with the first information input of the third switch, the second information input of which is connected to the output of the third adder, the first input of which is connected to the output of the first shift unit, the second input of the third adder is connected to the output of the second adder, the second information inputs of the first and second switches are connected to the outputs of the first and second, respectively clever residents.

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