SU1411768A1 - Device for solving logical equations - Google Patents

Abstract

The invention relates to computing, namely, devices for solving logical equations. The purpose of the invention is to improve the accuracy of the device by obtaining a minimum power solution. The device contains a counter 3, n groups of elements with m elements AND in each, where n is the number of variable equations; m is the magnitude of the coefficients of the equations, the operation unit 5, the comparison unit 6, the trigger 7, the HE elements 8 and 9, the AND element 13 and the memory block 14. The basis of the operation of the device is the formation of lexicographically ordered parameter values and the estimation of the solution at each step. 3 ill., 1 tab.

Description

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and

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SP) 00

The invention relates to a computational technique, namely, to specialized devices for solving logical equations,

The purpose of the invention is to improve accuracy by obtaining a minimum power solution.

FIG. 2 shows the diagram of the device j. FIG. 3 is the diagram of the comparison block,

The device contains inputs - 1 coefficients — device equipments j input If, the right side of the device equation, outputs 2 result of device j counter 3, groups 4 with the first I – O elements I, operational unit 55, comparison unit 6, trigger 7; the first 8 and second 9 elements are NOT, the outputs 10 of the sign of the absence of a solution. Equation of devices and the output of 1 sign of the presence of a solution of the equation of the device; clock input device 12; element 13, memory block 14. Operational unit 5 contains adders 15 modulo 2, outputs 16 of the operational unit. Comparison unit contains elements Equality 17, And element 18.

The device works as follows.

The device is designed to solve logical equations of the form

H. at

:-to,

1 T

mm

where A. is the i-e-ga bit binary

word;

n - the number of binary words and, accordingly, the number. variables; x e 0.1

B is a binary word 5 corresponding to the right side of the equation.

The solution of the equation is to determine the set x fx ,, .. "jX of minimum power satisfying this condition,

Depending on the binary code coming from the output of counter 3, signals 1 are output from the memory block 14 in the respective positions, and the position numbers that are formed for each state of counter 3 are graphically ordered. The table shows an example of the formation of a combination.

000 001 010 100

01 101

by

P1

5 20 25 30

five

five

0

from the table v, it is valuable that at the beginning of the form. combinations of one element, then two, three, etc.

The inputs 1 1 j are supplied with the binary words A, ,,., Respectively

Input 1 is supplied with the binary word B, (the jth bit of all binary words having weight 2 is fed to the jth input,. ,, „, j, m). In the initial state, the triggered ger 7 is in state 1, the binary counter 3 in the state Oo, ' 0. At the output of the memory block 14, the binary code is Ooo.OK. At the (n + 1) output of the binary counter, the signal is O, at the output of the HE element 9, therefore, after applying clock pulses through the element And the 13-pulses, the counter input of the binary counter 3 arrives its condition. The i-ro value of the output bit of memory block 14 corresponds to the value of x. If x 1, then the i- group of elements 4 opens, and a binary word enters the input of the operation unit 5; if x 0, the operation unit 5 calculates the expression

WITH

Ha.

by one-by-one addition, modulo 2 corresponding bits, arriving at its inputs of binary numbers.

Comparison unit 6 performs a bitwise comparison of numbers C and B. When

 At the output of the comparator unit 6, a signal 1 is generated, resetting the trigger 7 to the zero state. In this case, the element And 13 is closed, and the pulses do not go through the counting input of the binary counter 3 and do not change its state.

In the process of solving there may be two cases.

There is a solution to the equation. In this case, at output 11, a sign of the presence of a solution appears, and the value of the bits at outputs 2 of the result corresponds to the values of x,

There is no solution. In this case, after going through all 2 options, the binary counter 3 at the (n- -I) -M output generates a signal 1, and at the output 10 there appears a sign of no solution, through the element 9, the signal O arrives at the input of element 13 closing the flow of pulses to the counting input of the counter 3.

Claims (1)

Invention Formula A device for solving logical equations comprising a counter, an AND element, the first and second elements NOT, a trigger, an operational block, a comparison block, n groups of m elements AND, each, where n is the number of variable equations, m is the magnitude of the coefficients of the equation j-th input (C 1 ,, .. t) i-ro (, ...., p) of the equation coefficient of the device connection five To the first input of the j-ro element AND the i-th group, the output of which is connected to the j-th information input of the i-th group of the operation unit, the j-th output of which is connected to the j-th input of the first group of the comparison block, j-th input the second group of the comparator unit is connected to the jth input of the value of the right side of the device equation, the device clock input is connected to the first input of the element I, the output of which is connected to the counting input of the counter, the first information output of which is connected to the output of the sign of the absence of a device solution and to the input of the first element This is NOT, the output of which is connected to the second input of the AND element, the output of the comparison unit is connected to the counting input of the trigger, the output of which is connected to the output of the indication of the presence of a device solution and to the input of the second element NOT whose output is connected to the third input of the AND element, characterized in that In order to increase accuracy by obtaining a minimum power solution, it contains a memory block, with the second to (n + 1) -th information Q outputs of the counter being connected respectively to the address inputs from the first to the 5th memory block, entry chte which is connected to the clock input of the device, the i-th output of the memory block is connected to the i-th output of the device's decision result and to the second inputs m of the i-th group. 0 five 35 H 1t sixteen fPil2.2