RU1802409C - Reversible counter - Google Patents

Abstract

The invention relates to difference counting devices and can be used, for example, to count the difference of objects moving in opposite directions. The device contains input buses 1 and 2 and n counting bits (4-1,4-2, 4-3, ...). Each 1st bit contains a trigger, an AND element, and an OR element. 2 ill.

Description

The invention relates to difference counting devices and can be used, for example, to count the difference of objects moving in two opposite directions.

The aim of the invention is to increase the speed of the device. An additional goal is to eliminate the dependence of the device speed on the number of bits included in its composition.

Figure 1 shows a block diagram of an apparatus for the case where inter-bit transfer signals are generated from the inverse outputs of the triggers; Fig. 2 is a block diagram of an apparatus for the case where inter-bit transfer signals are generated from the direct outputs of the triggers.

As an example, a four-bit reversible counting device is presented, which contains the first 1 and second 2 input buses and counting bits 3, which are numbered in the order of increasing numbers I from low to high 4-1, 4-2, 4-3, 4 -4. In each 4-th section 4-1 contains trigger 5-1, element And 6-1 and element

OR 7-1. Numbering of inputs of elements AND - from top to bottom. Numbering of inputs of elements OR - from bottom to top.

In accordance with the claims, communications between device elements are made as follows. The output of the trigger 5-1 of each category (inverse in Fig. 1 and direct in Fig. 2) is connected to the first input of the element And b-i, the output of which is connected to the first input of the element OR 7-i, the output of which is connected to the counting input T-flip-flop 7-0 + 1) of the next 4-0 + 1) bit. The second inputs of the AND-6-I elements of all bits are connected to the first input bus of the device 1. The second inputs of the OR-7-i elements of all bits and the counting input of the T-trigger 5-1 of the first bit are connected to the second input bus of the device 2. In contrast from the prototype, the output of the element And b-i of each i-ro of category 4-i is connected to the 0 + 2) inputs of the elements OR 7-0 + 1), 7-0 + 2), ... of all subsequent bits 4-0 + 1), 4-0 + 2), .... For example, the output of the AND 6-1 element of the first category 4-1 is connected to the third inputs of the OR elements 7-2. 7-3 .... second

ate

00

about y

oh oh

and subsequent bits; the output of AND element 6-2 of the second category 4-2 is connected to the fourth inputs of OR elements 7-3, 7-4, ... of the third and subsequent bits, etc.

Input buses 1 and 2, when counting objects, can be connected to the outputs of the respective sensors. The initial state of the device is set by applying a pulse single signal to the input Set O before starting work. In this case, all 5-I triggers are set at the input R to the zero (off) state when the potential single signal is present at the inverse output, and the potential zero signal at the direct output. The simultaneous action of signals on buses 1 and 2 is not allowed. Tires 1 and 2 are tires of partial 1 and full 2, respectively.

The device operates as follows.

The complete reversal operation is carried out in the device upon termination of the action of a single signal on the complete reversal bus 2. In this case, a single signal from bus 2 is fed to the counting T-input of trigger 5-1 and then through the second inputs of OR elements of the previous bits to the counting inputs of triggers of subsequent bits (from the output of the OR 7-1 element to the counting input of trigger 5-2, from the output of the OR element 7-2 to the counting input of the trigger 5-3, etc.). At the end of the action of a single signal on the bus 2 of the trigger 5-1, 5-2, 5-3, ... switch to the opposite state.

The zero partial access operation is performed only for the device of FIG. 1. With the appearance of a single signal on the partial access bus 1, it arrives at the second inputs of AND elements of all the counting bits. The effect of this signal is manifested at the outputs of AND elements of only those counting bits whose triggers store a zero value. From the output of the And element of the very first, starting from the youngest, a bit storing a zero value; the signal enters through the OR elements to the counting inputs of the triggers of all subsequent bits. At the end of the action of a single signal on the partial access bus 1, these triggers switch to the opposite state.

A single partial access operation is performed only for the device of Fig. 2. With the advent of a single signal on the partial access bus 1, it arrives at the second inputs of AND elements of all the counting bits. The effect of this signal is manifested at the outputs of AND elements of only those counting bits whose triggers

store a single value. From the output of the And element of the very first, starting from the lowest, a bit storing a unit value, the signal enters through the elements

OR to the counting inputs of the triggers of all subsequent bits. At the end of the action of a single signal on the partial access bus 1, these triggers switch to the opposite state.

The difference in the operation of the calculating device when performing operations of zero and single partial circulation is due to the different types of triggers used to implement these operations. At

5, the circuitry is the same.

If the device provides (Fig. 1) operations of partial and full reversal, then to increase the module

0 of the result stored in the counting device, it is necessary to send a signal first to the bus

1 partial, and then to the tire 2 of complete circulation; in order to reduce the module of the result stored in the meter, it is necessary to first apply a signal to the full bus 2, and then to the partial access bus 1.

If the device provides (FIG. 2) single partial and

0 of complete circulation, in order to increase the module of the result stored in the meter, it is necessary to first send a signal to the full bus 2, and then to the partial bus 1, and to reduce the modules of the result stored in the meter, it is necessary to first send the signal to the partial bus 1, and then to the bus

2 full circulation.

In this case, the signal duration should

0 exceed its propagation time over the logical elements of the device. The pause time between input signals must exceed the trigger switching time and the logic return time

5 elements of the device in the initial state.

Since double partial or double complete reversal of the result stored in the counting bits does not lead to a change in this result, after two signals arrive on one of the buses 1 or 2 of the device, the result stored in its counting bits remains the same.

The listed features in work

5 of the counting device make it possible to use it together with two sensors without any intermediate between the sensors and the counting device elements for counting objects, objects, particles, marks, marks, etc.

In this case, it is possible to calculate both their number if they move relative to the sensors in one direction (summation, subtraction), and the difference in their number if they move relative to the sensors in two opposite directions. The implementation of any of these options (summation, subtraction, reverse counting) is the same. It is enough to send signals from the outputs of two sensors to two corresponding buses 1 and 2 of the device. When fixing an object (object, particles, tags, risks, etc.) twice with the same sensor (the corresponding object went beyond the range of one sensor, did not reach the zone of the active sensor and returned), the result in the proposed calculating device remains unchanged.

Suppose that the bits contain the initial result 0101, the contents of the smallest bit are indicated on the right, and the oldest - on the left,

To increase the contents of the bits (Fig. 1) by one, the operation of zero partial reversal of the initial result is carried out first. An intermediate result 1001 is obtained in bits. A complete reversal operation is performed with the obtained intermediate result. The final result 0110 is obtained in bits, one greater than the original. In order to reduce the contents of the bits by one, a complete inversion operation is carried out with an initial result of 0101. An intermediate result 1010 is obtained in bits. A zero partial reversal operation is performed with the obtained intermediate result. The final result 0100 is obtained in bits, one less than the initial one.

In order to increase the contents of the digits (Fig. 2) by one, the operation of complete reversal of the initial result 0101 is carried out first. The intermediate result 1010 is obtained in the digits. A single partial reversal operation is performed with the obtained intermediate result. The final result 0110 is obtained in bits, one greater than the original. In order to reduce the contents of the bits by one, a single partial call operation is performed first with the initial result 0101. An intermediate result 1011 is obtained in bits. A complete reversal operation is carried out with the obtained intermediate result. The final result is obtained in bits 0100, one less than the initial one.

When the contents of 1111 count bits are increased by one, the final state of the bits is the state 0000. When the contents of 0000 bits are reduced by one, the final state is the state 1111.

Feasibility

from the use of the invention is

in improving device performance and

eliminating performance dependencies on

number of bits.

The performance of the device (both proposed and selected as a prototype) can be estimated by the minimum time between successive input signals Tmin. If the speed of the elements AND, OR, triggers is taken to be approximately the same and denoted by m, then for the proposed device

Caraway seeds 6G.

since, in accordance with the description of the operation of the device, the duration of the input pulse signal must exceed 3 g, and the pause duration must also exceed

3 g (for the worst case, when the signal comes from input bus 1). In addition, for the inventive device, Cmin is independent of the number of bits of the converter.

Based on the description of the prototype

Caraway. (2 g 4-2t) -n, where n is the number of bits of the prototype device (for the worst case, when the signal comes from input bus 8 and passes through the OR elements of all bits, switching the triggers of all bits.

The speed of the prototype, therefore, is lower, the more it contains bits.

Performance gains could be

2

estimated by the number - n, which shows in

ABOUT

how many times the frequency of the input pulses of the proposed device can be higher than the frequency of the input pulses of the prototype

(provided that the proposed device and prototype are implemented on the same elemental base and have the same number of bits). A gain is observed with a number of bits of two or more.

Techno-economic indicators, such as the expansion of the scope and increase in the productivity of the systems comprising the proposed device, are derivatives of improved performance.

The description is based on the condition that the output signals are removed from the direct outputs of the triggers.

Claims (1)

The claims A reversible counting device containing an AND element, an OR element, and a trigger, the output of which is connected to the first input of the AND element, the output of which is connected to the first input of the OR element, the output of which is connected to the counting input of the trigger of the next category, the second inputs of AND elements all bits are connected to the first input bus devices, the second input of the OR element and the counting input of the trigger of the first category are connected to the second input bus of the device, characterized in that, for the purpose of increased performance, the second inputs of the OR elements of the second and all subsequent bits are connected to the second input bus of the device, the output of the AND element of each i-ro bit is connected to the (+2) th inputs elements OR of all subsequent bits. Dov. Јh /. 2