SU1651377A1 - Up-down counting device - Google Patents

Abstract

The invention relates to differential counting devices. Purpose — Expansion of functionality and application area by providing reverse counting of pulses fed to separate buses. Can be used both autonomously for differential counting of pulses fed through separate buses, and in conjunction with sensors 1 and 2 214 for differential counting. objects (particles, labels, scratches) moving relative to the sensors in opposite directions. The presentation of the counting results is possible in the forward, reverse and complementary with flax codes The device contains a reversible counting node 3, each bit 4-1,. "., 4 of which is made on the counting trigger 5-1,.", 5-n, elements 6-1, ooo, 6-n and the element OR 7-1, „,,, 7-п, as well as partial tires 8 and full 9 inversion. An input node 10 is inserted into the device, equipped with inputs I, 12, 13, 14 connected to tires 8, 9, 15 and 16, respectively, and the outputs 17 and 18, which are the inputs of, respectively, the partial and complete reversal of the reversible counting node 3. The input node 10 is made on the elements OR 19-1 and 19-2, the driver 20-1 and 20-2 and canbe provided with control inputs 21-1 and 21-2 2 Il. (L 05 ate with |

Description

The invention relates to differential counting devices and can be used to calculate the difference in the number of pulses coming in two separate tires, to calculate the difference of objects (marks, scratches) moving in opposite directions, or to count the number of objects moving in one direction. Lenia (in the mode of summation or subtraction) „

The aim of the invention is to expand the functionality and application areas of a reversible counting device by providing a reversible counting of pulses arriving on separate buses.

Figures "1 and 2" show the variants of using the device for calculating the difference in the number of pulses generated by two sensors (m, for differential counting of pulses arriving on the left of the separate buses).

The device can be used to work in conjunction with the first 1 and second 2 sensors, while it includes a reversible counting node 3, each bit 4-1 "." And which contains a counting trigger 5-1os, 5- p, element Hi 6-4..o6-p, and the element OR 7-1 „„ о7-п0 The output of the element OR 7-i is connected to the first input of the element OR 7- (1-D) of the next bit, the second input of the element OR 7-1 is connected to the output of the AND 6-1 element of this bit 4-i, the first inputs of the AND elements of all 6-1 “.6-n bits are combined, the second input of the element Ib-i is connected to the output of the counter trigger 5-t data discharge of 4-1, 5-1 counting trigger input connected to the first input of the OR 7-1 i of the discharge 4-i. The device also includes partial bus 8 and full 9 treatment and input input node 10, the first 11, second 42, third 13 and fourth 14 inputs of the input node are connected respectively to the partial conversion bus 8, full access bus 9, the first counting bus 15 and the second counting bus 16, and the first 17 and second 18 outputs of the input node 10 are connected respectively to the combined first inputs of the AND 6-1 ... 6-p elements of all bits 4-1. „„ 4-п and to the first the input element OR 7-1 first 4-1 bit.

The input node 10 contains the first 19-1 and second 19-2 elements OR, the first inputs of which are connected respectively to the first 11 and second J2 inputs of the input node 10, and the outputs of elements 19-1 and 19-2 are connected respectively to the first 17 and the second 18 outputs of the input node 10. In addition, the input node JO contains two shaper 20-1 and 20-2, and the input and output of the first shaper 20-1 are connected respectively to the third input 13 of the input node 10 and the second input of the second element OR 19- 2 input nodes 10, and the input and output of the second driver 20-2 are connected respectively naturally to the fourth input 14 of the input node 10 and the second input of the first element OR 19-1 of the input node 10,

The input node I0 contains the first 21-1 and. the second 21-2 control inputs connected respectively to the third inputs of the first 19-1 and second 19-2 elements OR input node 10.

In this case, if the sources that generate signals to the inputs 41-14, 21-1 and 21-2 of the input node 40 allow for the combination of the outputs, the elements OR 19-1 and 19-2 can be performed according to the principle INSTALLING OR.

The output 17 of the input node 10 is an input of the partial reversal of the reversible counting node 3, the output 48 of the input node 10 is the input of the complete reversal of the reversible counting node 3,

The reversible counting unit 3 shown in Fig. 1 provides for performing operations of zero partial inversion (after the expiration of the pulse signal from the output 17 of the partial inversion) and full inversion (after the expiration of the pulse signal from the output 18 of the full inversion) „

The reversible counting unit 3 shown in Figo 2 provides for performing operations of a single partial treatment (upon expiration of the pulse signal from the output 17 of the partial circulation) and full circulation (after the expiration of the pulse signal from the output 18 of the full circulation).

The difference in the work of the reverse counting node 3 when performing opera

The zero (Fig., 1) and unit (Fig, 2) partial references are caused by the different types of triggers used to implement these operations. In this case, the circuit solution is the same.

The full call operation (Figs. 1 and 2) provides for the inversion of the state of the flip-flops of all countable bits (4-1 "4").

The zero partial inversion operation () provides for the inversion of the state of the flip-flops of all those high 4- (iH)., 4-n bits that follow the least significant bit 4-i storing a zero value. At this, the state of the flip-flops is Dov 4-1o0 „4-i remains single

The operation of a single partial reference (Fig. 2) involves inverting the state of the flip-flops of all those higher 4- (i + l) ". 4-n bits, which follow the least significant bit 4-i, which stores the single value. In this case, the trigger state of the 4-1 o-bit discharges 4-1 remains zero,

If the device provides (figo) zero partial and full access operations, then to increase the module stored in the reversible counting node 3, the signal must be sent first to the partial output 17 and then to the full circulation output 18, and to reduce the stored module in the reverse counting node 3 results it is necessary to give a signal first to the output 18 of the full, and then to the output 17 of the partial circulation.

If the device provides (fig.2) a single partial and full call operation, to increase the module stored in the reversible counting node 3, the signal must be sent first to the full output 18 and then to the partial conversion output 17, and to reduce the stored module in the reverse counting node . 3 results it is necessary to give a signal first to the output I7 of the partial, and then to the output 18 of the full access.

In this case, the duration of the signal must exceed its propagation time through the logical elements of the device. The duration of the pause between

ten

15

25

20

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the input signals must exceed the switching time of the triggers and the time of returning the logic elements of the device to the initial state.

The simultaneous action of the signal at the outputs 17 and 18 of the reverse, counting node 3 is equivalent to the action of the signal at output 18 only and results (at the end of the action of the signal) to perform a full reversal operation

Sequential receipt of two pulse signals at one of the outputs (17 or 18) leads to a double partial (if the signals arrived at output 17) or double full (if the signals arrived at output 18) addressing the contents of the counting bits of the reversing counting node Zo. effects of two signals received successively in time on one of the outputs (17 or 18) of the reverse counting node 3, the result stored

in his countable bits, remains the same

Consider the operation of the reverse counting node 3 in the implementation of the operations of full circulation, zero partial circulation and a single partial circulation

five

five

The full access operation (Figures 1 and 2) is carried out in a reversible counting node 3 upon the termination of the signal at the output of the full access output 18. With the appearance of the signal at output 18, this signal along the circuit - 0 hence the connected elements OR 7-1 .... 7-P goes to the counting inputs of the flip-flops 5-1.5-p all counting bits. Since the first inputs of the elements OR, 7-n signals are missing, then at the end of the signal at output 18, the signals at the counting inputs of the flip-flops 5-1 ,. .5-n all countable bits disappear, which causes them to be shifted to the opposite state

The operation of the zero partial This step (Fig. 1) is performed in a reversible counting node 3 upon termination of the signal at the output 17 of the zero partial inversion. With the appearance of the signal at the output 17, it is fed to the first inputs of the elements AND 6-1.o6-n of all countable bits. The effect of this signal appears on the outputs of the elements

five

And only those

counting bits whose triggers store a zero value. From the output of the AND element of the very first, starting with the youngest, of 4-1, storing a zero value, the signal arrives at the second input of the OR element of this counting bit 4-1. connected elements OR the signal arrives at the counting inputs of the triggers of all counting bits 4- (1 + 1) ... 4-n following the very first, starting with the youngest, counting bit storing a zero value. Upon termination of the signal at output 17, the signals at the counting inputs of the 5- (1 + 1) ... 5-p flip-flops do not change, and the 4- (1 + 1) ... 4-n counting-bit triggers switch to the opposite state, and the state of three heras remains single.

The operation of a single partial circulation (Fig. 2) is performed in the reversible counting node 3 upon termination of the signal at the output D 7 of the single partial circulation. With the appearance of the signal at the output J 7, it is fed to the first inputs of the AND 6-1 elements. of all countable bits. The effect of this signal appears on the outputs of the elements. And only those countable bits whose triggers store a single value. From the output of the element And the very first, starting with the youngest, bit 4-i, storing a single value, the signal arrives at the second input of the OR element of this countable bit 4-1 Next along the chain of series-connected elements OR the signal goes to the counting inputs of all the trigger points counting bits 4- (1 + 1). 4-n, following the very first, starting with the youngest, the discharge storing the single value. After the end of the signal action on vmhope 17, the signals on the counting inputs of the 5- (1 + 1) flip-flops, the triggers of the 4- (1 + 1) ... 4-n counting digits disappear and switch to the opposite state, and the trigger status of 5-1 ... 5-i remains zero.

The listed features in the operation of the reversible counting node 3 allow it to be used in conjunction with the input node of the TO to implement a variety of functions.

Reversible counting device can operate in different modes 5 0

5 0 5 O 5 0

five

value counting of items and differential counting of pulses.

In the differential counting mode, items of the bus 15 and 16 of the reversing counting device, as well as the inputs 13 and 14 and the formers 20-1 and 20-2 of the input node are not involved in the operation of the elements OR J 9-D and 19-2 of the input node 10 provide for the transmission of signals from inputs 21-1 and 24-2 to outputs 17 and 18, respectively, and to the reversible counting node 3 With respect to sources of signals, objects (labels, risks) move in opposite directions When moving relative to the sensor of an object (no matter in which direction he moved) from the exit The sensor produces a pulse. The sequence of arrival of pulses from sensors J and 2 determines the direction of movement and, as a result, in the countable bits of the reversing counting node 3, either an increase or a decrease by a unit of stored result is recorded. In this mode, it is necessary to ensure the separation of objects actions of sensors When an object was fixed twice with the same sensor (it indicates that the object went beyond the action area of one sensor, did not reach the action area of another sensor, and returned again) the result in the account This device remains unchanged. In this mode, it is also possible to count the number of objects moving relative to the sensors in one direction, and the calculation can be carried out either by summing the objects or by subtracting the objects.

In the differential pulse counting mode (Fig. 1), a differential counting of pulses from the outputs of the sensors 1 and 2 pulses is provided. In this case, any devices that produce these pulses can be considered as sensors. In this mode, the output of one sensor is connected to the integrated bus 8 of partial access and the first counting bus 15, the output of the other sensor is connected to the integrated bus 9 of the full access and the second counting bus 16.

When the signal from the output of the first sensor 1 through the first

the input and output of the first element OR 19-1 of the input device 10 enters the output 17 of the partial reversal of the reversing counting node 3 and disappears at this output only after the signal disappears at the output of the sensor. As a result, a partial reversal (zero in FIG. and a single one in FIG. 02) 0 After some time (slightly longer than the time of switching the triggers and returning the logic elements to the initial state) along the delayed falling edge of the signal, the first one is shaper 20-1 producing At its output there is a signal which, through the second input and output of the second element OR 19-2 of the input device 10, arrives at the output I8 of the complete reversal of the reversing counting node 3 and disappears at this output only after the signal disappears at the output of the driver, As a result, in the reverse the counter node implements a full access operation. Thus, in a reverse counting device on the FNG, 1 module of the stored result was increased by one, and in a reverse counting device on it was decreased by one

When a signal is received from the output of the second sensor 2, it is fed through the first input and output of the second element OR 19-2 of the input device -10 to the output 18 of the complete reversal of the reversing counting unit 3 and disappears at this output only after the signal disappears at the sensor output, B As a result, a full access operation is implemented in the reverse counting node. After some time (slightly longer than the switching time of the flip-flops and returning the logic elements to the initial state), the second driver 20-2 generates at its output a signal that through the second input and output of the first element OR 19-1 of the input device 10 enters output 17 of partial inversion of the reversing counting node 3 and disappears at this output only after the signal disappears at the output of the imaging unit. As a result, the operation of the partially reversing counting node of treatment (FIG zero "and the unit 1 in Figure 2) o Thus, the reversing device counting module stored on Figol result was reduced by one, while reversing the counting device in Figure 2 uvelichils unit ,,

The use of the device shown in Fig. 2 is, for a number of cases, more preferable, since the operation of a partial partial processing is equivalent to converting the direct code of the stored number into an additional one and it is possible to present the counting results on the same outputs of the trigger points. forward, reverse and additional codes.

The presentation of the counting results on the same outputs in different codes can be implemented for the subsequent digital processing of these results.

Managing the presentation of counting results in various codes can be done from inputs 21-1 and 21-2 of the input node.

It should be noted that the simultaneous arrival of signals at the outputs 17 and 18 of the reversing counting node is generally prohibited and is equivalent to the effect of the signal only at output 18. Accordingly, it is necessary to ensure time separation of signals arriving at the input device, 10,

Let us consider with examples how the increase and decrease by one unit of the result stored in the countable bits is achieved when implementing pair operations of zero partial and full inversion, as well as single partial and full inversion

Let the discharge result contain the original result 11, 0101, the contents of the least significant bit are indicated on the right, and the oldest one - on the left.

If in the reverse counting node 3 (Fig. 1), operations of zero partial and full circulation are provided, then in order to increase the content of the bits by one, first, the operation of zero partial conversion of the initial result is performed. An intermediate result, CO ,, 1001, is obtained in bits. With the intermediate result obtained, the operation is carried out with complete access. Receive in time

A series of the final result of L. oooOPO is one unit larger than the initial value. To reduce the contents of the bits by one, the initial result is performed, O0101, first, the full treatment operation. The intermediate result is obtained in the bits. OOoooooooooooooing. in bits, the final result is 1100 „0100, one less than the original

If in the reverse counting node 3 () single partial and full circulation operations are provided, then in order to increase the content of the bits per unit, first complete conversion of the initial result 11 00 004 OJ is carried out. Intermediate result is obtained in bits OO.oolOJOo With the obtained intermediate result, unit partial inversion operation. The final result IK ,, 0140 is obtained in the bits, one unit larger than the initial one. To reduce the content of the bits per unit, the initial result is 11 °. 0101 first partial operation unit handling Prepared bit intermediate result rows oJOil 00o C obtained intermediate result comprising the step of complete discharge handling is obtained in rows 11 on the final result "0100, one less than the starting

When increasing the content of Jo to ol111 countable bits per unit, the final state of the bits is state 00 "" 0000 When decreasing the contents of 00 "0000 bits, the final state is state

The technical and economic effect of the use of the invention lies in expanding its functionality and, as a result, in expanding its areas of application. The proposed device provides offline differential counting of pulses arriving at separate inputs, and together with two sensors, differential counting of objects moving in opposite directions, or counting their number when moving objects.

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in one direction (by summation or by subtraction) This provides a representation of the counting results on the same outputs of the reverse counting node in the forward, reverse, and additional codes

Claims (1)

Invention Formula A reversible counting device containing partial and full circulation buses and a reversible counting node, each digit of which contains a counting trigger, an AND element and the OR element, the output of which is connected to the first input of the OR element of the next bit, the second input of the OR element is connected to the output of the AND element of this bit, the first inputs of the elements AND of all bits are combined, the second input of the element AND of each bit is connected to the output of the counting trigger of the given bit, the counting the input of which is connected to the first input of the element OR of this bit, characterized in that, in order to expand the functionality and application areas by providing reverse counting of pulses arriving on separate buses, it additionally contains an input node, first, second, third, fourth inputs of the input node la connected respectively to the bus the first and second outputs of the input node are connected respectively to the combined first inputs of the AND elements of all bits and to the first input of the OR element of the first bit, the input node contains the first and second elements OR, the first the inputs of which are connected respectively to the first and second inputs of the input node, .a outputs of which are connected respectively to the first and second outputs of the input node, and two delayed pulse shapers with a dynamic inverted trigger input, the input and output of the first shaper are connected respectively to the third input of the input node and the second input of the second OR element, and the input and output of the second shaper are connected respectively to the fourth input of the input node and the second input of the first OR element, and the input node also contains the first and second control inputs, which are connected respectively to the third inputs of the first n of the second elements OR of the input node, the first counting bus and the partial revolution tire are combined, and the second counting bus is combined with the full speed bus. shu