SU594530A1 - Shift register storage cell - Google Patents

Description

The invention relates to computing and can be used to construct shift registers. A shift register is known, built on the M-S system and containing two RS-flip-flops, one of which is the main one, and the second one is additional, each of these triggers has two controls, together with which it forms a memory cell 1. Each cell consists of the four elements of AND-NOT (OR-NOT). The disadvantage of this register is a large number of elements and a large number of inputs in the elements, which complicates the shift register circuit. Closest to the proposed technical entity is a memory cell containing AND-NOT elements, the output of the first AND-NOT element is connected to one of the inputs of the second AND-NOT element, the output of which is connected to one of the inputs of the first AND-NAND element, and clock bus 2. The disadvantage of this memory cell is a large number of elements per bit. For each bit, eight two-input AND-NOT elements are used. simplification of the scope of the invention. This is achieved by the fact that in the memory cell another input of the first element is NOT connected to the clock pulse bar, another input of the second element IS NOT connected to the input of the cell and to one of the inputs of the third element IS NOT the other input of which is connected to the output of the second element is NOT, and the output of the third element is NOT connected to the output of the cell. The drawing shows a schematic diagram of the proposed device. The memory cell contains three AND-NOT elements. Perhaps the use of equivalent items OR NOT. Each register bit is made on two memory cells. The first bit is executed on the cell containing the elements AND-NOT 1, 2 and 3, and on the cell containing the elements AND-NOT 4, 5 and 6. The second is made on the cell on the elements AND-HE 7, 8 and 9 and on the cell on I-NE elements 10, 11, and 12, the third bit — on I-H1 elements; -: 13, I, 15, 16. 17 and 18. The device contains IIHIHI I clock pulses 19, 20, and a go peiHCTpa 21 .

In each cell, the output of the first element is connected to the input of the second element, the output of which is connected to one of the inputs of the first element. Each cell contains a clock bus 19, 20, with the inputs of the first elements 1, 7 and 13 odd cells connected to the bus 19 clock pulses, and the inputs of the first elements 4, 10 and 16 even cells are connected to the bus 20 clock pulses. In the cell, the input of the second element 2 is connected to the input of the cell and the input of the third element 3, so the input of element 2 is connected to the input of the register 21 and to the input of element 3, the input of element 5 is connected to the input of the second cell, which is connected to the output of the first cell, i.e. . to the output of element 3 and the input of the third

element 6 cells. The second input of the third cell element 3 is connected to the output of the second cell element 2. The output of the cell is the output of the third element 3.

A parallel code from a register can be removed from the outputs of elements 1, 7, 13, 2, 8, 14 and from elements 4, 10 and 16, 5, 11 and 17.

Consider the operation of the device, provided that the scheme used elements of NAND for positive pulses at the input.

A feature of the register on the proposed memory cells is that in each of its memory cells at the output of the third element since the arrival of the negative clock on the clock bus (s) of a given cell and before the arrival of the negative pulse on the clock bus of the previous one, its memory cells there is a high potential.

Indeed, if the memory cell, suppose 7, 8, 9, was in a state with a high potential at the output of element 7 and low at the output of element 8, then at the output of element 6 a high potential had to act after the arrival of a negative pulse on the bus 19 the trigger state (not highlighted in the drawing) on elements 7 and 8 does not change and at the output of element 9 due to the low potential at the output of element 8 there will be a high potential.

If the trigger on elements 7 and 8 was with a low potential at the output of element 7, then two potential variants are possible at the output of element 6. At a high potential at the output of element 6 with the arrival of a negative impulse to the bus 19 at the output of element 7, high potential at the output of element 8 - low, which will cause at the output of element 9 high potential.

With a low potential on the element output; 6 at the output of element 9 due to the action of this potential at its input, a high potential will be maintained regardless of the potential at the output of element 8.

Now suppose that the previous air memory cell was in a state with low potential at the output of element 5 and high at the output of elements 4 and 6, then with the arrival of a negative impulse to the bus 19, the next cell at elements 7, 8, 9

will take the same state, i.e. at the output of elements 7 and 9 there will be a high potential, and

output element 8 - low. With the arrival of a clock pulse on the bus 20, the same state will be overwritten into the next cell on the elements 10, 11, 12.

If the previous memory cell on elements 4, 5, 6 was in a state with high potential at the output of element 5 and low at the output of element 4, then when a pulse arrives at the bus 19, all the inputs of element 6 will have high potentials and at the output of element 6 there will be a low potential, which at the end of the pulse on bus 19 will set the cell at elements 7, 8, 9 to a state with high potentials at the outputs of elements 7 and 9 and low at the output of element 8.

The next impulse, arrival on bus 20, will rewrite the information from cell 7, 8, 9 into cell 10, I, 12.

Thus, after each arrival of clock pulses on bus 19 and 20, the information is changed into two memory cells.

The number of elements in the proposed memory cell is reduced by 25% compared with the number of elements in the known memory cells. In the proposed cell, three elements are used, while in the known cells four are used.

Saving items in memory cells reduces the amount of hardware, cost, power consumption and increases device reliability.

Claims (2)

1. Bukreev I.N., Mansurov B.M. and Gorchev V.I. Microelectronic circuits of digital devices. M., “Owls. radio, 1975, p. 85, fig. 3.7. and rice 3.8. 2. Bukreev I.N., Mansurov B.M. and Gorchev V.I. Microelectronic circuits of digital devices. M., “Owls. radio, 1975. with. 82, fig. 3.3. nineteen one