SU1651302A1 - Reversible counter - Google Patents

Description

FIG. one

The invention relates to apparatus. You need a differential account (direct, reverse, or reverse) and can be used in the systems of counting signals from sensors for automatic control at a non-binary conversion factor.

The purpose of the invention is to simplify the device,

Figure 1 shows the block diagram of the device; Fig. 2 shows examples of the implementation of counting bits for the case when triggers with inverse outputs are used; Fig. 3 is the same for the case when triggers with direct outputs are used.

In Figs 1-3, the following definitions are accepted: 1 — first input bus or first sensor; 2 - second input bus or second sensor; 3 - counting node containing counting bits modulo 21 4-1: 4-p.

The revolving counting device contains the first 1 and second 2 sensors and the reversing counting node 3, each bit 4-1 ... 4-n of which contains a counting trigger 5-1 .., 5-n, And 6-1 elements ... 6-p, elements OR 7-1 ... 7-p. The output of the element OR 7-i is connected to the first input of the element OR 7- (i +) of the next bit, the second input of the element OR 7-i is connected to the output AND 6-i of this bit 4-i, the first and second inputs of which are connected respectively with the output of the first sensor 1 and the output of the counting trigger 5-i of the given bit, the counting input of which is connected to the first input of the element OR 7-i of the given bit, which in the first bit 4-1 is connected to the output of the second sensor 2.

The outputs of sensors 1 and 2 are partial buses 8 and full 9

five

0

5 Q

0

five

the older mth (5th 4-5) are connected with the entered third inputs of a part of the first K () low-order bits of this group, namely with the introduction of the third inputs of the AND 6-1 and 6-3 elements of the first 4-1 and third 4-3 bits. In this case, the conversion factor of such a group of bits is equal to 22.

The number of m bits required to realize a conversion factor of 21 (where 1 is an odd number) is generally chosen at the nearest greater degree of the number 2. For example, for our case when 21 is 22, the nearest integer of the number 2 is 32. Therefore The required number of bits is 5, since 32 25.

The least significant bits, at the input of the third inputs of the elements And of which feedback is organized from the output of the element OR m-ro of the discharge, are determined by the difference converted into binary code. The feedback is organized into those bits of the difference represented in binary code that contain 1, for example, for our case, a 5. The number 5 translated into binary code is recorded as 101 (2 ° 1.2 0, 2 1 ). Consequently, the feedback is organized at the input inputs of the elements AND bits 4-1 (2 °) and 4-3 (2).

It should not be forgotten that in this case the pulse recalculation is carried out in a code with an excess of -1 over a ring of 21 states (for our case in a code with an excess of 5 around a ring of 22 states).

Table 1 presents the data necessary for the synthesis of a reversible counting device with a conversion factor of 21, where 1 is an odd number (up to). This table does not

50

circulation The simultaneous action of sig-45 included conversion factors 2, 4, 6,

8, 36, 32, -64, since they are implemented by known devices without feedback. This table also did not include conversion factors of 12, 20, 24, 28 - 2 “14, 36 2x1 8; 40 2 2 10; 44 2x22, 48 2x2x12- 52 56, 60, 68, 72, as they are implemented by factors that are either in table 1 or are an integer power of 2, implemented without feedback.

Using the above rule, this table can be continued until

The load on tires 8 and 9 is equivalent to the effect of the signal only on tire 9. The output of the element OR 7-p is the output 10 of the counting bit.

The device uses triggers that switch on the falling edge of single signals at their counting inputs.

To achieve this goal in each group of consecutive bits (in Figures 2 and 3, a group of bits for the case when, including bits 4-1 ... 4-5), the output of the element OR 7-5

55

5165

in Thus, the proposed reversible counting device allows counting on any even-numbered module.

The operation of the device is based on the operations of full circulation, zero partial circulation and single partial circulation.

The full access operation is performed in the device at the end of the signal on the full access bus 9. At the same time, with the appearance of the signal on the bus 9, this

the signal on the circuit is sequentially connected (5 triggers 5-1 .., 5-n, in which the signal

non-OR elements 7-1 ... 7-p of all countable bits 4-1 ... 4-p goes to the counting inputs of the 5H ... 5-P triggers of all counting bits. Since the triggers 5-1 ... 5-n echo over the falling edge of the signals arriving at their counting inputs, switching of the triggers 5-1 ... 5-n does not occur. Since at the first inputs, the output of the transfer is present, if the trigger stores a single value (figure 2), and is carried out as follows, With the appearance of a signal on the 20 8 partial reversal spike, it arrives at the inputs of the AND 6-1 elements ... 6 -in all 4-1 ... 4-n countable bits. The effect of this signal is manifested at the outputs of the elements And only for those countable dimensions OR 7-1 ... 7-n signals of the absence of 25, the triggers of which are stored one, then at the end of the action of the signal 9 complete reversal on the counting inputs of the triggers 5-1 ... Zt1 all 4-1. . .4-n counting bits disappear, which causes the switching of triggers 5-1 ... 5-n of all 4-1 ... 4-n counting bits to the opposite state.

The zero partial access operation provides for the use of 35

value. From the output of the element And the very first, starting with the youngest, counting bit, storing a single value, the signal is fed to the input

30 elements OR of this countable bit. Then, along the chain of series-connected elements OR, the signal goes to the counting inputs of the triggers of all the counting bits following the very first one, starting with the youngest, counting bit, which stores the unit value. Since the triggers 5-1 ... 5-n are switched on the falling edge of the signals arriving at their counting inputs, then

triggers 5-1 ... 5-p, in which

the signal at the output of the transfer signal is present if the trigger stores a zero value (Fig.), and is implemented as follows. With the appearance of a signal on the bus 8 of partial inversion, it arrives at the inputs of the elements AND 6-1 ... 6-n of all 4-1 ... 4-n countable bits. The effect of this signal is manifested at the outputs of the elements And only for those countable bits whose triggers store a zero value. From the output of the AND element of the very first, starting with the first, the bit storing the zero value, the signal arrives at the input of the OR element of this countable bit. Next, the chains of series-connected elements OR the signal goes to the counting inputs of the triggers of all the counting bits following the very first one, starting with the youngest, counting bit, which stores the zero value. Since the triggers are switched on the back front of signals arriving at

their counting inputs, then the switch does not occur. Upon termination of a single signal on a partial inversion driver 8, the signals at the counting inputs of the triggers of all counting bits following the very first one, starting with the youngest, counting bit storing the zero value, become zero, and the triggers of these counting bits switch to the opposite condition.

The operation of a single partial call involves the use of

at the output of the transfer is present, if the trigger stores a single value (FIG. 2), and is carried out as follows. With the appearance of a signal on the partial access spike 8, it arrives at the inputs of the AND 6-1 elements ... 6-p all 4-1 ... 4-n countable bits. The effect of this signal is manifested at the outputs of the elements And only for those countable bits whose triggers store a single

value. From the output of the element And the very first, starting with the youngest, counting bit, storing a single value, the signal is fed to the input

the OR of this countable bit. Then, along the chain of series-connected elements OR, the signal goes to the counting inputs of the triggers of all the counting bits following the very first one, starting with the youngest, counting bit, which stores the unit value. Since the triggers 5-1 ... 5-n are switched on the falling edge of the signals arriving at their counting inputs, there is no switching of the triggers. going on. Upon termination of the single signal on the partial-inverting bus 8, the signals at the counting inputs of the flip-flops of all counting bits following the very first one, starting with the youngest, counting bit storing the unit value, become zero and the triggers of these counting bits switch to the opposite condition.

The difference in the operation of the counting device when performing operations of zero and single partial circulation is due to the heterogeneity of the triggers used to implement these operations. If the device provides (Fig. 2) zero partial and full access operations, then to increase the module stored in the counting device.

In order to achieve the result, you must first send a signal to the partial bus 8, and then to the full access bus 9, and to reduce the result stored in the counting device, you must first send a signal to the partial call 9, then

If the device provides (FIG. 3) for a single partial and full call operation, then to increase the module of the result stored in the counting device, it is necessary to send a signal first to the full call and then to the partial call bus 8, and to reduce the result stored in the counting device it is necessary to give a signal first to the bus 8 partial, and then to the bus 9 full circulation.

At the same time, the duration of the signal must exceed its propagation time through the logical elements of the device. The duration of the pause between the input signals must exceed the switching time of the flip-flops and the time of returning the logic elements of the device to its initial state.

Since a double partial or double complete inversion of the result stored in the counting bits does not change this result, after the arrival of two signals on one of the buses 9 or 8 of the device, the result stored in its counting bits remains the same.

These features in the operation of the counting device make it possible to use it together with two sensors 1 and 2 without any intermediate elements between the sensors and the counting device for counting objects, objects, particles, marks, notes, etc. In this case, it is possible to count both their numbers if they move relative to the sensors in one direction (summation, subtraction), and differences in their numbers if they move relative to the sensors in two opposite directions. The implementation of any of these options (summation, subtraction, reversible counting) is of the same type. It is enough for the two corresponding tires 8 and 9 of the device to signal from the outputs of two sensors 2 and 1. When an object is loosened (object, chaggits, tags, risks, etc.), the same

ten

15

20

25

thirty

35

40

45

50

55

however, the sensor (the corresponding object went beyond the zone of action of one sensor, did not reach the zone of action of another sensor, and returned) the result of the proposed accounting device remains unchanged.

Let the discharge result contain the initial result I ... 0101, the contents of the least significant bit are indicated on the right, and the oldest one - on the left.

To increase the content of the bits (Fig. 1) by one, the zero partial inversion of the original result is first performed. An intermediate result of 00 ... 1001 is obtained in bits. With the intermediate result obtained, a full access operation is performed. A final result of 11 ... 0110 per unit greater than the initial one is obtained. To reduce the contents of the bits per unit, the initial result of 11 ... 0101 is performed first with the full access operation. An intermediate result of 00 ... 1010 is obtained in bits. With the resultant intermediate, the result is a zero partial conversion operation. A final result of 11 ... 0100 is obtained in bits, one less than the initial one.

In order to increase the content of the bits (Fig-2) per unit, the operation of completely reversing the original result 11 ... 0101 is carried out first. An intermediate result of 00 ... 1010 is obtained in bits. With the intermediate result obtained, an operation of partial partial circulation is carried out. The final result, AND 1 ... 0110, is obtained in bits, one greater than the initial one. In order to reduce the contents of the bits per unit, the initial result of 11 ... 0101 is carried out, first the operation of a single partial reference. An intermediate result of 00 ... 1011 is obtained in bits. With the intermediate result obtained, a full access operation is performed. The final result P ... 0100 is obtained in bits, one less than the initial one.

When increasing the contents of 11 ... 1111 countable bits per unit, the final state of the bits is the state 00 ... 0000. Bree decrementing the contents of 00 ... COOC bits per unit. The final state is state 11 ... 1111.

Thus, differential calculation of objects modulo 216, i.e. in binary code.

The difference in the operation of the proposed device lies in the fact that each group of m bits works in its (generally different) state ring. Before starting, the triggers of those bits that contain the AND elements with the entered third ones (the inputs are set to one state, and the remaining triggers are set to zero.

For example, for the case of FIGS. 2 and 3 in a group of m 5 bits, the triggers 5-1 and 5-3 are set to one state before starting work, and the rest are set to zero.

The subsequent work of the group from the bits in Figures 1 and 2 is explained in Table 2 of the transitions. Table 2-1 indicates the enabled state and O indicates the disabled state of the corresponding triggers for each of the conditions of the group. Since the recalculation is carried out in a code with an excess of 5, the conditional state of the group is always 5 less than the binary weight recorded in bits 4-1 ... 4-5.

In accordance with the transition table, a group of bits 4-1 ... 4-5 recalculates a ring of 22 conditional states, numbered from 0 to 21. At the same time, transfer signatures are generated to the countable bits of the following groups the transition from the 21st state to the 0th when forwarding and the transition from the 0th state to the 21st when counting down. For any other transitions, a signal is formed twice at the output 10 of the element OR 7-5, providing double complete reversal of the subsequent bits, as a result of which they remain in the same state as before the signals were received. At the indicated transitions (from the 0 to the 2G state and vice versa), the effect of the signal on bus 9 leads to the complete reversal of

bits, and the action of the signal. a NOT ging 8 - to a partial (zero partial in FIG. 2 to a single partial ng, fig. 3) treatment following the group of bits. This provides the formation of the transfer signal for the next group of discharge.

Claims (1)

Invention Formula A reverse counting device containing the first and second input buses and a counting node, each counting bit modulo 21 (which is odd, in general, is a common bit for each bit) which contains gfcfc. triggers, elements AND and elements OR (n is the smallest number that satisfies the condition 2m), the output of each K-th (K, 2, ..., h) count-; the first trigger is connected to the first input of the K-th element AND, the output of which is connected to the first input of the K-th element OR, whose output (except for m-ro) is connected to the counting input of the (K + 1) -th counting trigger, the second input of the first element And is the first input of the counting bit, the counting 1 of the doubles of the counting trigger is the second input of the counting bit, the output of the i-th element of the IPY is the output of the counting bit and is connected to the second input of the next counting bit, So that, in order to simplify the device, the counting input of the K-th counting m The igger is connected to the second input of the K-th OR element, the second input of the first element AND is connected to the second inputs of the second and subsequent AND elements, the output of the Mr. element OR is connected to the third inputs of those AND elements whose numbers coincide with the unit positions of the number 2 1, represented in binary code, where the lower position of the binary number is considered to be the first, the first inputs of all countable bits are connected to the first input bus, and the second input of the first account of the logo bit is connected to the second input bus 9 8, 9 8 9 8 9 8 9 8 9 8 9 8 9 8 9 8 9 Table 1 table 2