SU612413A1 - Reversible counter - Google Patents

Description

one

The device relates to radio engineering and is intended for automation and computer systems.

The known reversible counter, each bit of which contains inverters connected to a counting trigger, the output of which is connected to the transfer chains of addition and subtraction, the inputs of which are combined with the inputs of inverters, does not allow to get the counting results in the forward code 1.

Of the known reverse meters, the closest device to the invention is a device containing serially connected command disjunctor, inverter pulse generator, code disjunctor, code trigger and demand conjunctor, the second input of which is connected to the interrogation bus, and the inputs of the command djjunctor are connected via command reversal trigger tires, and summing counter, each discharge of which contains a serially connected disjunctor, counting thrngger and conjunctor, connected by its output to the disjunk input ora subsequent discharge, -with this second inputs and dizyuiktorov koiyunktorov soednneny yield PFN handling and conjunctor significant bit output coupled to another input of codeword

a disjunctor, with a counting input of a sign trigger and a third input of a disjunctor and a low bit, the first input of which is connected to the input signal width 2.

The known reversible counter allows to obtain the result of the counting in the forward code, which, however, is destroyed when read, and this prevents the use of the known device in systems where the counting continuity must be maintained.

The aim of the invention is to provide non-destructive readout information) in a direct code.

Claims (2)

This is achieved by the fact that in a reversible counter, containing successively connected dzjunktor commands, inverter pulse generator, code disjunctor. code trigger and polling conjunctor, the second input of which is connected to the polling bus, the command disjunctor inputs are connected to the command buses via the reverse trigger, and the summing counter, each bit of which contains series-connected disjunctor. countable trngger and conjunctor. A connected output with an input of a discharger of a subsequent discharge, wherein the second inputs of disjunctors and conjunctors are connected to the output of the inverter pulse generator, and the output of the higher-order conjunctor is connected to another input of a code disjunctor, as well as to the counting input of the sign trigger and the third input of the disjunctor low-order bit, the first input of which is connected to the input signal bus. An AND - OR logic element is introduced, the output of which is connected to the input of the command disjunctor, and the triggers are connected to the recovery signal bus and to the outputs of the trigger and reverse trigger, respectively. The drawing shows a functional diagram of the reverse counter. The proposed reversible counter consists of a summing counter, each discharge of which contains a series-connected disjunctor, a counting trigger 2, and a conjunctor 3, connected by its output to the inputs of the disjunctor 1 of the subsequent discharge. In addition, several commands are disassembled sequentially, driver has 8 calls, 5 code points, 7 code trigger KOHbsoHKTop oorsa 8, the other input is interfaced with Sh oiros 9, and the output is connected to the input of d18junker – 4-d Tr gg-p of the reverse 10 is connected to a co-ordinate folding system II and calculated 12. Signal input 13 is connected with a secondary input of a junior f of the low-order bit counters. The output of the inverter pulse inverter 5, is connected to the second inputs of the conjugators 3 to the disjunction I of each bit and the number of counters. The output of the conjunctor 3 of the highest bit is connected to another input of the code disjukctor 6. with the third input of the disjunctor I of the junior discharge and with. the counting trigger input sSiaKa 14, connected to the Sasz & outputs from the pair of inputs of the AND-OR 15 logic element, two other pairs of inputs of which are connected respectively to the output of the 16N reverse trigger with the REST signal BUS 16 The output of the AND-OR circuit 15 is connected to one T Inputs of the command disjunctor 4. Before the start of the counting, the reversible counter is set to the initial state, in which the counting currents 2 of the summing counter are set to zero, the trigger 7 closes conjunctor 8, the trigger state of the reverse 10 corresponds to the summation mode vania, and the state of the trigger 14 corresponds to a positive number in the reverse flow tag. If, prior to the arrival of the counting kmggulieu, the bus 11 is given a command to be summed up 1e, then the trigger of the reverse 10 does not change its state, and the result of summing up the counting pulses arriving at input 13 is represented in the counter in the forward code. At the same time, at the moment of time before reading, the polling pulse arriving via bus 9 does not pass through the polling controller 8, as a result, the information recorded in the counter is read without additional conversions in the forward code. A recovery impulse arriving on bus 16 at the next time point after reading, the element AND-OR 5 passes through, closed by potentials from the outputs of the reverse trigger 10 and the sign trigger 14. If, after summing m pulses, command subtraction 12 is given, then the trigger the reverse 10 changes its state and through the disjunctor of commands 4 starts the formatter 5. The circulation pulse coming from the output of the imaging unit 5 through disjunctors I changes the state of the counting-. triggers 2 on the reverse, the translation recorded in the summing counter number m in the reverse code | 2 -t-1 |. The same pulse for eliminating the transfer pulses for the time of circulation closes conjunctors 3 and changes the state of the trigger through the disjjctor ft, from which the coyunk 8 opens. The following subtracted to the impulses received at input 13 are summed up with the reverse code numbers t, accumulated in the mode of addition. As a result, the code | 2 (t-gc) is 1 in the counter. 1. At the time of BpesseHBs, before reading, the polling pulse through connector 8 and disjunctor 4 starts shaper 5, the pulse of which reverses the code of the number written in the counter. As a result of the code reversal, the number (tk) w- remains in the counter (C and the readout of txl (tk) is made in the direct code. If 8 is the initial state, before the arrival of the counting pulses, bus 2 is sent to bus 2 , then the state of the trigger of the reverse 10 changes, shaper 5 starts, code triggers are opened to code triggers and zero is generated in the counter in the return race (III ... I). At the next moment of time, the first subtracted count pulse arrives on input 13, an overflow of the pulse. An overflow pulse with an output the high-order conjunctor 3 places the trigger 14 into the state corresponding to the counter number in the counter, and through the disjunctor 6 by means of the code trigger 7 closes, the conjunctor 8, and through the low-order disjunctor 1 the unit writes down the one. e unit in the counter so that it contains the number of the (-) K, where the hook is | y., the mustache (signk (- t) l is stored in the {4. At the moment before the match, the demand pulse does not cause the code to be reversed and the information is read in the direct code without loss of language. In this case, as in the case of summation, the restoration impulse passes through the AND-OR 15 element, which is closed by the trigger triggers of the reverse and the 10 and 14 sign, which, however, have changed theirs by that moment. CONDITIONS. If after the subtraction to the pulses via the com-dayline H, the addition and addition command is given, the pesepca 10 trigger changes its state and turns off the disjunctor 4 the imaging unit 5 starts. The reversal impulse converts the recorded Ellfunction in the counter into the return code (1) The no. Opens the coyunkter 8. With the following summing up, the first m of the lines, arriving at the input 13, are emitted with the inverse code of the number K. accumulated in the subtraction mode. At the same time, the code (- (k-t) -1) is written in the counter, and the sign (-1) is saved at the trigger 14 at 14. Before the reading, the polling pulse reapplies the number written in the counter. As a result of the repeated inversion the code (-1) (k-t) remains in the counter and the number is read in the forward code. After reading the information with the preliminary treatment of codes, the next continuous counting of pulses in the considered cases is as in the subtraction mode after the addition (the first case), so and in the mode of “add” and after subtraction (the second case ) before the supply of recovery pulses becomes impossible. This is due to the fact that, for example, in the first case, with further subtraction in the counter, f-pulses will be added to the number (t - / s) in the counter, and the counter will be written in the counter. ) instead of (t - “-). In the transition to the summation of E pulses will be added to the inverse code of the number (tk), and as a result, the number (tk -) - - 1 will be written in the counter, which after the treatment does not correspond to the correct reading result (tk + t). In the second case, with further summation after subtracting, I pulses will be added to the number (k-t) and the number (-1) X (k-m + t) will be written in the counter instead of (-1) (k-m-O; to the subtraction of the number I will be added to the inverse code of the number (k-t) and as a result the number (-1) will be written in the counter (2 (k-ha-O-IJ) which after the treatment does not correspond to the correct reading result (-1) ( k-t4-. Thus, reversing a code before reading results in such a change in the information in the counter that the lack of recovery schemes does not allow for a continuous t pulses. In other words, if in a reversible counter after summation, subtraction is performed followed by reading and inequality (mk) 0 is satisfied or after subtraction, summation is performed and inequality (k-t) 0 is fulfilled, then information may be destroyed. eliminating the possible destruction of information in reading and ensuring the continuity of pulse counting, the AND-OR logic element 15 is input. The output of the AND-OR element 15 is connected to the input of the disjunctor 4, and three pairs of inputs are connected respectively to the bus 16 and to the outputs t the signers and the reverse of the 10 and 14. Both in the first and in the second case, after reading the inversion of the codes, the triggers 10 and 14 are in such a state that they open one of the two AND elements as part of the AND-15 logical element with their potentials. and the recovery pulse, the passage through the AND-OR element 15 and the disjunctor 4, produces a code inversion that restores the information. After such a recovery, continuous counting of pulses can be continued without zeroing the counter. Indeed, in the first case, the count (t / s) after rebuilding the conversion is converted into reverse (t / s) -1): Upon further subtraction of 1 pulse, the number (.) -1 is recorded in the counter, which, when read after repeated circulation matches the correct result (tk-t). When summing, the reverse code obtained with this recovery is converted into a forward code (tk) and summation of f occurs. impulse As a result, a number (tk + E) appears in the write counter 1 and the correct reading occurs. - Similarly, in the second case, the code (-1) (k-t) after a reversal is converted to F type (-1) 2 - (k-ni) -1. During the subsequent summation of i Sov B the number (-) {2- (k-m-1) - I is written to the counter, which, when read after re-accessing, corresponds to the result (-1) (k-t). When subtracting, the reverse code obtained by recovery is converted to forward (-1) (c-rp) and the t-pulses are summed. As a result, the number (-1) (c-m + C) and the error are recorded in the counter. correct reading. Claims of the invention A reversible counter containing serially connected command disjunctor, address pulse shaper, code disjunctor, code trigger and polling conjunctor, the second input of which is connected to the polling bus, the inputs of the command disjunctor through the reverse trigger are connected to the command wiring, and the summing counter, each time which contains serially connected disjunctor, counting trigger and conjunctor, connected by its output with the disjunctor input of the subsequent discharge, while the second inputs are conjuncturers and conjunctors are connected to the output of the inverter pulse generator, and the output of the higher-order conjunctor is connected to another input of the codedjunctor, as well as to the counting input of the sign trigger and the third input of the junior disjunctor, the first input of which is connected to the input signal bus, differing that, in order to ensure non-destructive reading of information in the forward code, a logical element AND-OR is introduced, the output of which is connected to the input of the disjunctor of commands, and three sets of inputs are connected respectively with shiioy reduction signal and the outputs of flip-flops and reversing the sign. Sources of information taken into account in the examination: 1. USSR author's certificate number 372698, M. KL.2 H 03 K 21 / iO, 05.01.7L 2. USSR author's certificate number 414744, M. class. H 0.3 K 23 / {Yu. 03.20.72. & W) 90LT yy AND : 7 av