SU762201A1 - Recounting device - Google Patents

Description

The invention relates to measuring equipment, in particular, to digital recording devices.

A multi-decade counting device of direct and reverse accounts is known [1], 5

containing reversible counter, comparison unit, counting decade, switch block

The disadvantage of this scheme is the absence of the possibility of a sign preset. ten

The closest to this technical solution is the device [2], which contains a counter, a control device connected to the control inputs of the digit write keys, switch blocks, the lower counting decade, OR, AND prohibition elements, a decoder connected to the lower counting outputs decades, the preset node. The decoder outputs are connected via the first switch block with bitwise write keys connected to the counter, the first input of the lower counting decade through the first OR element and the AND element are connected to the clock bus, the installation 25 inputs of the lower counting decade are connected to the second block through the preset node switches that are connected to a control device to which the zero setup input 30 is also connected

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the youngest counting decade. The second input of the first element OR is connected through the prohibition element to the device input, the second output of the lower counting decade through the prohibition element and the OR element, the second input connected to the zero input of the preset node, is connected to the input of the counter, and the second inputs of both prohibition elements are connected to the control inputs of bitwise write keys.

The disadvantage of this device is the lack of a sign algebraic preset counter, ie, the possibility of adding the insertion number and the residual value of the counter.

The aim of the invention is the expansion of functionality, which consists in the possibility of sign presets.

This goal is achieved by the fact that the device containing the reversible counter, the control unit, the switch block, the clock, the element And, entered the mode definition block, additional counter, comparator and trigger, the first and second pulse inputs and control input block definition mode, as well as a single trigger input are device inputs, two outputs of the mode detection unit

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connected to the corresponding pulse inputs of the control unit, the clock input of which is connected to the output of the clock pulse generator, whose input is connected to the trigger output, the first and second control inputs of the control unit are connected respectively to the output of the And element and the control output of the switch block, and the output to the reverse input the counter, a group of outputs of which is connected to a group of inputs of the element I, the input of an additional counter is connected to the output of a clock generator, and the group of its outputs and output in the switch unit connected to the corresponding inputs of the comparison unit; the output of the latter is connected to a single trigger input.

The drawing shows a block diagram of the device.

The device contains input buses 1 and 2, a mode detection unit 3, pulse buses 4, 5, a control unit 6, a clock generator 7, a multiple-input element AND 8, a trigger 9, a binary-decimal reversing counter 10, a display unit

11, a block of buffer amplifiers 12, an output of a block of buffer amplifiers 13, an additional counter 14, a comparison block 15.

The device works as follows.

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Two groups of successive rectangular pulses that are shifted in phase by 90 ° are fed to inputs 1 and 2, which, through the mode definition block 3, uniquely determine the phase advance or lag mode. If the impulses arriving at bus 1 are ahead in phase by 90 ° the impulses arriving at bus 2, then the output 4 of the mode definition block 3 produces a series of pulses, and during a phase lag pulse appears on bus 5.

The pulses received on the bus 4 and 5, are fed to the input of the control unit 6.

20 In the control unit 6, the operation mode of the binary decimal reversing counter 10 is determined depending on the counter sign.

Possible cases of changing the mode of operation are shown in the following table.

The state of the phase of the pulses on the bus 1, the pulses on the bus 2 Counter sign Mode of operation of the control unit Advance Addition Lag "+" Subtraction Advance "4" I Subtraction Lag "- · Addition

The pulses from the output of the control unit 6 are fed to the input of the binary-decimal reversing counter 10. Thus, the pulses fed to the input of the binary-decimal counter 10 are added with a positive sign pre-recorded in the number counter, and when the pulses are ahead on the bus 1 pulses on bus 2, or with a negative sign, pre-recorded in the number counter, and when the phase of the pulses on the bus 1 pulses on the bus 2.

The zero outputs of all the triggers of the binary-decimal reversible counter 10 are connected to the multi-input element And 8.

At the time of transitions of the reversible counter 10 through zero at the output of the multi-input element And 8, a low potential appears, which is fed to the input of the unit pack _{; 1} P; ^and W9 ^and H1 M>, ° T timing

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until a low potential appears at the output of the multi-input element And 8. The outputs of the binary-decimal reversible counter 10 is connected to the inputs

30 display unit. At the same time, the outputs of the reversible counter 10 are connected to the inputs of the buffer amplifier 12 for outputting 13 to digital printing.

The device has the ability to input any decimal number into the reversible counter 10, which happens as follows.

In the switch block 5, the required number is dialed with a “+” or “-” sign for 40 inputs to the reversing counter 10. When a low potential is applied to the bus 17 (trigger input 9), the trigger 9 is set to one and the clock pulse 7 is excited. Im45 pulses simultaneously arrive at the input of a binary decimal counter 14 and at the input

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the control unit 6 is fed to the input of the binary-decimal reversible counter 10 in the addition or subtraction mode.

At the moment when the value of the BCC counter 14 equals the number dialed in the switch block 5, a low potential is obtained at the output of the comparison block 15, which sets the trigger 9 to the zero state, as a result of which the clock pulse generator 7 is blocked.

Thus, the number dialed in the switch block 16 and the number in the binary-decimal reversible counter 10 are added algebraically.

When the input pulses are fed into the mode definition unit 3 and the low potential quadrupling 16 is simultaneously applied to the bus, the input pulses are formed into a series of counting pulses whose frequency is four times higher at the input pulses.

Claims (3)

Claim A scaling device containing a reversible counter, a control unit, a switch block, a clock pulse generator, an AND element, characterized in that, in order to extend the functionality, which consists in the possibility of a sign algebraic design settings, a mode definition block, an additional counter, a comparison block and a trigger are entered, with the first and second pulse inputs and the control input of the block 5 mode detection, as well as a single trigger input are device inputs, two outputs of the mode detection unit are connected to the corresponding pulse control unit inputs, clock 10 whose input is connected to the output of the clock generator, whose input is connected to the trigger output, the first and second control inputs of the control unit are connected respectively to the output of the And element and to the control output of the switch block, and the output to the input of the reversible counter, the output group of which is connected to a group of inputs of the element And, the input of the additional counter is connected to 20 output of the clock, and a group of its outputs and outputs of the switch block are connected to the corresponding inputs of the comparator, the output of the latter is connected to a single trigger input. 25