SU725072A1 - Device for determining maximum number from a series of numbers - Google Patents

Description

g (54) DEVICE FOR THE DETERMINATION OF MLZYMDLIYOGO

.- I

NUMBERS FROM A NUMBER OF NUMBERS

The invention relates to computing and automation and can be used in the processing of information.

According to the main author. St. 432490, a device is known for determining the maximum number of a number of numbers containing an adder, two "1-bit reversible counters, each of which information input is connected to the output of the corresponding AND circuit, one input connected to the input device, and OTHER - to the output of the corresponding of the first I.LI circuit, the input of which is connected to the output of the second-bright OR circuit, input | which are connected to the outputs of the corresponding reversible counter, as well as a synchronous switch, each of two outputs of which is connected to the control input of the corresponding reversible counter and the input of the OR circuit of another reversible counter, the outputs of both reversible counters are bitwise connected to the inputs of the adder, whose outputs are connected to the outputs devices. This device . allows for the analysis of a number of consecutively incoming negvMod

the numbers and upon its completion to receive at the output the maximum number from those received from on ala7 analysts and 11.

However, using a known device, it is not possible to determine which number from the beginning of the analysis is the maximum that happens. It is necessary, for example, when estimating the signal level in parallel communication channels at different frequencies or during automatic antenna switching, to determine the direction to the radiation source.

The aim of the invention is to enhance the functionality of the device by determining the number of the maximum number in a sequence of numbers.

The goal is achieved

0 in that the third and fourth circuits of the AND circuit are entered into the device, the third counter, the pulse shaper, the information rewriting node, the memory node, and the outputs of the synchronous switch

5 of the main device is connected to the input of the imager, the first output of which is connected to the first input of the third AND circuit, the second input of which is middle with the output of the fourth circuit 0 and whose inputs are connected to the outputs of the first and second OR circuit of the main device, the output of the third AND circuit is connected to the control the input of the information rewriting node, which infry interfaces are connected to the 15th meter, the information input of which is connected to the second output of the pulse generator, the output of the information rewriting node is connected inputs of memory node, setting inputs of the counter and the memory node connected to a bus initial installation.

The block diagram of the device is represented on the drawing.

The device contains AND 1 and 2 circuits, reversible counters 3 and 4, synchronous switch 5, OR 6-9 circuits, cyiviMaTbp 10, AND 11 and 12 circuits, 13 PNU shaper, counter 14, information rewriting node 15, memory node 16, the input bus 17, the bus 18 installation. ,

The device works as follows.

At the beginning of the analysis of a number of numbers, the first number, represented by a series of pulses, is supplied, for example, through a two-binary AND circuit 1 to the input of counter 3, which is switched to the summation mode by a synchro switch 5. At the output of the circuit AND l will be a series of pulses, which represent: 1o number, in the ground, while at the second input of the circuit AND 1 there is a signal from the output of the synchronous switch 5, applied to the circuit AND 1 through the circuit OR 7. Counter 4 synchronous switch 5 transferred to the subtraction mode and at this time does not work, since there are no pulses at the output of the AND 2 circuit.

The absence of pulses at the output of the AND 2 circuit, which is fed to one of its inputs along the input bus, is ensured by the absence of the HS signal from another input of the AND 2 circuit via the OR circuit b. The inputs of the circuit b do not receive a signal from the output of the synchronous switch 5 or a signal from the output of the circuit or 8, the inputs of which are connected to the outputs of the reversible counter 4. In the next cycle, the counter 4 is switched to the summation mode, and the counter 3 - to the subtraction mode. With

this on one of the inputs of the circuit AND

1 is present- a sital from a yohad a -circuit OR 7, - fed along the circuit: output-. s reversible counter. 3 is an OR 9 - cxeMli OR 7 scheme. An input bus, which serves as the second input of the AND 1 circuit, is fed to a series of pulses representing the number

the output of the circuit And 1 will be a series of pulses: on one of the inputs of the circuit And 2 there is a signal from the output of the synchronous switch 5,; filed through the scheme OR b; pulses are given at the input fault.

/ -. .

representing numbers; to the input of counter 4 no & Tynaef a series of pulses.

In counter 4, a record is made and in counter 3, the next number is subtracted. If the number to be subtracted is greater than OR to the number 3 equally distant in the counter, then counter 3 goes to the zero state, while the signal at the output of the AND 1 circuit is absent because the signal from the output of the OR 9 circuit disappears, and its inputs are connected to the outputs of the reversible counter 3 If the number to be subtracted is less than the number that was previously recorded in the counter, then there will be a residue at the end of the subtraction, as a result of which one of the inputs of the AND circuit 1 will contain a signal j fed through the circuit: the outputs of the reversible counter 3 — OR circuit 9 —the circuit OR 7, preparation infusing that. the most counter. to write the next number. Upon receipt of the next number, represented by a series of pulses, to the input of counter 3 through the circuit And 1 it is summed with the remainder.

Before the input of the device of the analyzed numbers, a code corresponding to zero is recorded in the counter 14 and the memory node 16. When a consecutive number of numbers is input to the input, the synchronous switch 5 at both outputs generates voltages converting the reversible counters 3 and 4 alternately in addition and subtraction modes. These voltages are fed to the input of an impulse generator 13, which, when a voltage appears. Compound on any of the inputs, generates a pulse at each of the outputs.

A pulse arriving at the input of the slider 14 changes its state by one. The impulse arriving at the input of the third circuit And 11, passes to its output, only if there is voltage at the other input of the circuit connected with the output of the circuit and 14. Circuit I .14 generates a voltage at the output in the absence of at least one of the signal inputs (conditional units) from the outputs of the OR 8 and 9 circuits, which corresponds to the zero state of at least one of the reverse, counters 3 and 4. When the presence of a voltage on the output circuit of the AND 14 pulse from the output of the pulse forcing generator 13 passes through the AND 11 circuit to the control input of the information rewriting node 15, passing the code of the number written in the counter 14, to the memory node 16, Impulse to the driver impulses 1 connected to the input of the counter 14, several cuts a pulse at another output of the imager, thanks to which the state of the counter 14 at the time of rewriting has time to change

Claims (1)

Claim 5 Device for determining the maximum number of a number of numbers by ed. St. No. 432490, characterized in that, in order to expand the functionality of 10 by determining the number of the maximum number in the sequence ·. numbers, the third and fourth circuits AND are introduced into it, the third counter, the pulse shaper, the data rewriting unit, the memory node, and the outputs of the synchronous! switch of the main device are connected to the input of the shaper, the first output of which is connected to the first input of the third circuit And, the second the input of which is connected to the output of the fourth AND circuit, the inputs of which are connected to the outputs of the first and second circuits OR of the main device, the output of the third circuit And is connected to the control input * 5 of the house of the information rewriting unit, information inputs of which th connected to the output of the third counter, an information input coupled to the second output generator, 30 pulses, the output of the information rewriting unit is connected to the inputs of the memory node, the installation inputs of the counter and the memory node are connected to the initial installation bus.