SU1160360A1 - Device for correcting time scale - Google Patents

Description

The invention relates to navigation and telecommunications and can be used in systems for transmitting signals of the exact time.

The aim of the invention is to increase the noise immunity of the correction of the time scale.

FIG. 1 shows the electrical block diagram of the device for the correction of the time scale; in fig. 2 timing diagrams of signals explaining the operation of the device.

The proposed device contains a generator) I reference frequency, multi-lead delay line 2, switch 15 tor 3, frequency divider 4, third match 5, fourth match 6, third trigger 7, first trigger .8, first match 9, second trigger 10, second block 11 20

coincidence, counter 12 pulses, additional delay line 13.

Switch 3 contains a reverse shift register 14, blocks 15-17 matches, the element OR 18. 25

Device for the correction of the time scale works as follows.

When signals are received that correspond to the value of the time scale correction and the time scale correction mark, a correction value is written in the additional code to the pulse counter 12 and the third trigger 7 is set to the state corresponding to the correction mark, 35 preparing at This is the third block of 5 matches, or the fourth block of 6 matches.

The output signal of the first trigger 8 permits the passage of the phased-40 signals from the output of the additional delay line 13 through the first .. block 9 coincidences. By a negative differential of this signal, the second trigger 10 prepares, the second 11, <5

third 5 or fourth. 6 blocks of coincidence, depending on the sign of the amendment, to the passage of phased signals to the input of the counter 12 pulses and the first or second control input 50 of the switch 3.

Signals arriving at the first or second control input of switch 3 are respectively passed to the first or second control input 55 of the reversing shift register 14. The output from the corresponding discharge of the reversing shift register 14 is fed to one of the matching blocks 1517, which passes the signal from the corresponding output of the multi-split line 2 of the delay to the output element OR 18.

The output signal of the element OR 18 is fed directly to the input of the frequency divider 4, and through the additional delay line 13 to the second inputs of the third 5 and first 9 blocks of coincidence, as well as to the first input of the fourth block 6 of coincidence.

When the counter overflows 12 pulses at its output, a pulse is generated that arrives at the zero inputs of the first and second triggers 8 th 10, returning them to the initial state, due to which the second 11, third 5 and fourth 6 blocks of coincidences depending on the sign of the correction and phased signals pulse counter 12 and the reverse shift register 14 are not received.

FIG. 2 shows the timing diagram of the signals, explaining the operation of the device for the correction of the time scale. Diagrams a-e show the temporal relationship between the signals at the outputs of the split-line 2 delay. The switching moments of the delays of the multi-stream waterline 2 delay are carried out by the falling edge of the signal from the output of the OR 18 element delayed by the additional delay line 13 by an amount longer than the signal delay between two adjacent branches of the multi-port line ⁴ 2 delays. The limitation of the signal delay from above in the additional delay line 13 is determined by the signal's duty cycle. If the duty cycle signals

T

(where T is the repetition period; ΐ is the signal duration), then the signal delay in the additional delay line 13 will be Δ6 <b ₃ <

T - '·

<T --- ds. Plot and show moments

switching taps multi-line 2 delay in the case of a negative amendment, and plot to - in the case of a positive amendment. Regardless of the temporary position of the input signal, switching takes place when there are no signals on the switching taps of the multi-drop line 2 delays. By the time the signal appears, the third 5 or fourth 6 block of coincidence is already being prepared3

therefore, the waveform is not distorted. The waveform at the output of switch 3 is shown in plots w and h for the negative and positive corrections, respectively. "

Thus, the introduction of an additional delay line provides the phase-matching of the switching points of the taps of the multi-drop delay line.

1160360 4

to switched signals. Switching occurs when there are no signals on the switched taps, therefore the waveform is not distorted by 5 switching processes. The signals from the outputs of the bits of the reverse shift register, acting on the circuit of the switch, do not cause changes in the output potentials, which 10 increases the noise immunity.

figure 1

I

1160360

FIG. 2

Claims (2)

1. A DEVICE FOR TIME-SCALE CORRECTION, containing a series-connected reference frequency generator, a multi-tap delay line, a switch and a frequency divider connected in series the first trigger, the first match block, the second trigger and the second match block, the third trigger and the third match block sequentially, and also the fourth coincidence unit and a pulse counter, the output of which is connected to the combined zero inputs of the first 'and second triggers, the second input of the third coincidence unit is connected to the first input of the fourth coincidence block and the combined second inputs of the first and second coincidence blocks, the single input of the first trigger being the input of the device for entering the time-correction value, which is, in order to increase the Immunity correction, an additional delay line is inserted in it, while the output of the second trigger is connected to the third input of the third coincidence unit and the second input of the fourth coincidence unit, the third input of which is connected to the inverse output of the third trigger, the switch output is connected to the second input of the second coincidence unit whose output is connected to the input of the pulse counter, and the outputs of the third and fourth blocks of coincidence are connected respectively to the first and second control inputs of the switch pa, with the unit and zero inputs of the third trigger are respectively the first and "second additional inputs of the device for entering the sign of the amendment of the time scale. 2. The device according to claim. ^ Characterized in that the switch contains a reversible shift register, blocks of coincidence and the OR element, whose inputs are connected to the outputs of the corresponding blocks of coincidence, the first inputs of which are connected-. to the corresponding outputs of the digits of the reverse shift register, the second inputs of the matching blocks * are the information inputs of the switch, the first and second control inputs of the reverse shift register are the first and second control inputs of the switch, respectively, and the output of the OR element is the output of the switch. about 00 ABOUT) 1 1160360 2