SU1091171A1 - Digital extrapolating device - Google Patents

Abstract

DIGITAL EXTRAPOLATING DEVICE, socialized register, informational output of which is connected. with the first input of the element I, the output of which is connected to the first input of the first adder, the outputs of the absolute bits of the number of which are connected to the input of the converter, the code is the frequency whose output is connected to the clock input of the reversible counter, the control input of which is connected to the output of the sign bit of the first adder, the second input of which is combined with the information input of the register and is the information input of the device, the clock input of which is the second input of the element I. The information output is reversible The counter is an information output of the device, characterized in that, with an accuracy chain, a multiplier and a second adder, the output of which is connected to the installation input of the reversible counter, are entered into it, the first input of the second adder is connected to the output of the multiplier, the first input of which is connected to the outputs of the bits of the first adder, the second input of the multiplier is the input of the device coefficient, and the second input of the second adder combines with the second input of the first adder.

Description

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L. ) The invention relates to computing technology and can be used in computing devices that combine the extrapolation of a signal with the output signal from automatic control systems. A famous extrapolator (interpolating non-recursive digital filter) is known, which contains a memory device, a multiplier device and an adder that forms successively p output samples in the interval T between the output and output samples l. Such an extrapolator cannot be used for the correction of automatic control systems. Closest to the digital extrapolator proposed by the technical nature, which contains a memory register, the input of which is connected to the information input of the extrapolator, and the output is connected to the first input of the And element, the second input of which is connected to the clock input of the extrapolator, a parallel adder, The first input of which is connected to the output of the element I, the second input to the information input of an ecstrapor, and the first and second outputs of the adder are connected correspondingly with the third and fourth inputs of the reversible counter, the third output The adder is connected to the converter's input code — a frequency, the output of which is connected to the first input of the reversible counter, the second input of which is connected to the information input of the extrapolator, the output of the reversing counter, is the output of the extra field. In the adder of a known extrapolator, the first difference of the input signal, tg M (tt), is calculated, which is converted by means of a koc converter - frequency to the pulse frequency. The latter is fed to the input of a reversible counter, which performs the summation or subtraction of pulses depending on the sign of the first difference. The known extrapolator scheme is distinguished by its simplicity, speed and extrapolation accuracy, but the introduction of an extrapolator into the automatic control system impairs the system stability, reducing the phase margin, and therefore requires the use of special devices for correcting the dynamic parameters of the latter, which greatly complicates the system. The purpose of the invention is to increase accuracy. This goal is achieved by the fact that B a digital extrapolating device containing a register, information output of which is connected to the first input of the element I, the output of which is connected to the first input of the first adder, the outputs of the absolute part of the number of whose number are connected to the converter input code - frequency, the output of which connected to the clock input of the reversible counter, the control input of which is connected to the output of the sign bit of the first adder, the second input of which is combined with the information input of the register and is A multiplier and a second adder, the output of which is connected to the installation input of the reversible counter, are inputted to the information input of the device, the clock input of which is the second input of the AND element, the information output of the RB1 counter, the first input of the second adder is connected to the multiplier output, the first input of which is connected to the outputs of the bits of the first adder, the second input of the multiplier is the input of the device coefficient, and the second input of the second adder combines ene with a second input of the first adder. In addition to extrapolation, the device generates a correction signal N (n –SHPM (p) to achieve the specified dynamic parameters of the system. The drawing shows a functional diagram of a digital extrapolating device. The circuit contains a register 1, element I 2, first adder 3, converter code - frequency 4, reversible counter 5, second adder 6, multiplier 7. The device works as follows: Before the current value of the input code arrives, its previous value comes from the clock pulse arriving at The second input of the AND 2 element is rewritten into the adder 3, and the counter 5 is folded in. After that, the current code value is written to the register 1 and to the adders 3 and 6. In the adder 3 the first difference from the input code N (n) is calculated, the absolute value which is converted into a frequency in the converter code - frequency 4 and is fed to the input of the reversible counter 5, to the input of which a signal is received from the sign output of the adder 3 depending on the selected law

rivers (summation or subtraction of pulses). The calibration inlet of counter 5 comes from the output of the adder 6, which is the sum of the input signal and its first difference, taken from the previously selected coefficient, the largest of which is determined from the condition of the required control system quality indicators.

At the output of the reversing counter 5 through 10, a signal is transmitted

VNM.

(n) + o67Nt) lfl

wi

N (p) - input signal;

OS is a constant coefficient of intelligent.

resident;

m is the division factor of the converter; code is the frequency determined by the ratio of the quantization frequencies in time between the input and the output;

the number of the extrapolation segment within the quantization interval of the input signal;

coefficient determined by; the reference frequency of the transducer code is the frequency and the division factor.

The advantage of this device is that the type allows for combining extrapolation and linear correction functions in one device, for which a multiplier and a second adder with the appropriate connections are introduced into the circuit, which leads to an increase in accuracy.

Claims (1)

A digital extrapolating device containing a register, the information output of which is connected. with the first input of AND element, the output of which is connected to the first input of the first adder, the outputs of the digits of the absolute part of the number are connected to the input of the code - frequency converter, the output of which is connected to the clock input of the reverse counter, the control input of which is connected to the sign discharge of the first adder , the second input of which is combined with the information input of the register and is the information input of the device, the clock input of which is the second input of the element And, the information output of the reverse account Chika is an information output of the device, characterized in that, in order to improve accuracy, a multiplier and a second adder are inserted into it, the output of which is connected to the installation input of the reversible counter, the first input of the second adder is connected to the output of the multiplier, the first input of which is connected to the outputs of the discharges of the first adder, the second input of the multiplier is the input of the device coefficient, and the second input of the second adder is combined with the second input of the first sum of the torus.