SU1302295A1 - Phase filter - Google Patents

Abstract

The invention relates to digital computing and is intended for use in spectral analysis systems of processes with non-uniform frequency resolution. The purpose of the invention is to improve accuracy. The goal is achieved due to the fact that the phase filter consists of multiplexer 1, shift register 2, multiplexer 3, register 4, arithmetic unit 5, register 6 and synchronizer 7. 4 pcs. g kn 45/7 V ee tsD N5) L 9ig.1

Description

nn-1 ,, .., x (to the right is that of m from

., -

The invention relates to digital computing and is intended for use in spectral analysis systems of processes with non-uniform frequency resolution.

The aim of the invention is to improve the accuracy by implementing the correction of the frequency response of the filter.

Figure 1 presents the scheme of the filter j in figure 2 - the scheme of the arithmetic blockade of fig.Z - timing diagrams; figure 4 - diagram of the synchronizer.

The filter (figure 1) contains the first multiplexer 1, the shift register 2, the second multiplexer 3, the register 4, the arithmetic unit 5, the register 6 and the synchronizer 7.

The arithmetic unit 5 (FIG. 2) contains adders 8 and 9 and multiplier 10 and is intended to calculate the expression

A a (bc) + d,

The synchronizer 7 (Fig. 4) contains a clock pulse generator 11, a counter 12, a fixed memory block 13, delay elements 14 and AND elements 15

The device works as follows.

Let in the steady state operation in the first (left) bits of the shift register 2 be recorded some (n-1) -th values of the output function with the deformed spectrum. g,, ... .g,.,., (k is the order of the phase filter), and in the next tn next bits there are counts of the input sequence in the order of their arrival from right to left,,

accounts that came before the others). The contents of registers 4 and 6 are zero. At the first stage, the frequency composition of the input discrete process is corrected, compensating for the distortions introduced at the stage of the actual phase filtration. For this, the m samples of the input process, stored in the right bits of the shift register 2, are processed using a non-recursive frequency filter algorithm.

y

Fo -i i

(one)

where y is the i-th count of the output filtered sequence;

, (1 + l) -Y countdown INPUTS;

hj - j-th coefficient of the weight function f14ltra.

The value of the coefficients h; are chosen such that the ratio is

A, (f)

where A, (f) is the amplitude-frequency characteristic of the correction circuit;

Aj (f) is the amplitude-frequency characteristic of the device for phase filtering. Processing is as follows.

From the output of the last bit of the shift register, the i-ro value of the x-input process is transmitted to the first input of the arithmetic unit 5. At the same time, the fourth input of the block 5 from the synchronizer 7 receives the value b of the weight coefficient. Zero values are transmitted to the third and second inputs of the arithmetic unit 5 from the outputs of registers 4 and 6.

Obtained at the second output of the arithmetic unit 5, the value of the first partial sum S ,, equal to x; h, is received by the synchronizer 7 commands via the second multiplexer 3 to register 4 and is fixed in it. Then at the signal from synchronizer 7 to

shift register 2 shift occurs

one.

stored information for one bit

to the right. From the output of the last bit of the shift register 2, the value is deducted through multiplexer 1 to the released first bit of the register

A 2 shift and a signal from synchronizer 7 is recorded in it. In addition, this value is fed to the first input of the arithmetic unit 5 ,. to the second input of which a register x is transmitted from the output of the register 4; B, the third input is the zero value from the register 6 output, and the fourth input is the value of the corresponding weighting factor h, from the synchronizer 7 output. As a result, the output of the second partial Sj is equal to S, + x ;, h which, according to the signals of the synchronizer 7, through the second multiplexer 3 enters the register 4 and is fixed in it. Next by. signal

From synchronizer 7, the next shift of information in shift register 2 is performed and the next reading is processed. the input process is similar to the procedure described above, etc. Finally, after processing, the last count of the input process stored in shift register 2, in register 4, we get the filtered value of i-ro input- (snoring switch 2 is shifting snore “7 in

process

This count can be denoted by f. Then, according to the synchronizer signal and the shift register 2, the stored information is shifted to the right by one. bit, while the last (right bit of shift register 2 is shifted right intermediate go value, n-sequence with a deformed spectrum. In the first (left) bit of shift register 2 shift, synchronizer signals 7 receive and record the next value of the input process ( through the first) multiplexer 1 from its third input).

Then, a recurrent process of calculating the values of the sequence with the deformed spectrum at the next stage begins.

This process is described by

g

o, n

-G)

S i, n

 , n-, - o + f.,

 ., - o + g., j

(2) (3)

 chronizer 7. The values obtained at the output of the arithmetic unit 5 are fed to the input of register 6 and through multiplexer 1 to the input of the first bit of the shift register 2. The signals of the synchronizer 7 in the shift register 2 produce a shift

 aGg, -i 1 + b- (4) stored information to the right for one L ° i, n-i 01-1.n J s, -i У1-1)

discharge, and the coefficient put forward from the afterbirth is the coefficient determining the (right) discharge, g ,, the formation of the spectrum of the process (at 40 is recorded in register 4, and in the spectrum, the spectrum has a higher resolution ё 1, "1

Where

the value of g ,,,,, in the register 6 is written down the value of gi. Then, the next calculation takes place in the arithmetic unit 5, described by the expression (4), with, which occurs as a whole similarly to the processing presented above at the previous clock cycle, except for the third the input of the arithmetic unit 5 comes from the output of register 6 is not a zero value, and the value of g. Similarly, in accordance with expression (4), the samples of the sequence gi are calculated for all other values of i. Finally, as a result of performing the processing for the last k-ro count and getting it, we arrive at the initial

at low frequencies and lower at high frequencies, on the contrary - higher resolution at high and lower at low, with complex and time-45, the solution is increased in any pre-set region of the frequency range).

From the output of the last (right) bit of the shift register 2, the value g. Is fed to the first input of the arithmetic unit 5, to the second input of which the output of the register 4 transmits the value f, to the third the zero value from the output of the register 6, and to the fourth the code the coefficient of deformation of the spectrum a, specified from the synchronizer 7. At the output of the arithmetic unit 5, we obtain the value of the 0

sequence member with a deformed spectrum after the next iteration gj, which signals the synchronizer 7 through the first multiplexer 1 is fed to the input of the first (left) bit of the shift register 2. The output of the arithmetic unit 5 repeats the value of g. The signals from the outputs of the synchronizer 7 in re

15

The information to the right is one bit, while the value pushed out from the last (right) bit is written to register 4, and the value of g is fixed in the first (left) bit of register 2 shift.

20

Then, the g j value is calculated in accordance with expression (3). From the output of the last (right) bit of the shift register 2, the first input of the arithmetic unit 5 is transferred to the value g;, "; The second input of the arithmetic unit 5 from the output of the 25th register 4 receives the value 8 о, л-1 and the third is the zero value from the output register 6, and the fourth — the code value and the deformation coefficient of the spectrum specified from the synchronizer 7. The values obtained at the output of the arithmetic unit 5 of the device are fed to the input of register 6 and through multiplexer 1 to the input of the first bit of the shift register 2. 7 in shift register 2 is shifted

five

0

five

the value of g ,,,,, in the register 6 is written down the value of gi. Then, the next calculation takes place in the arithmetic unit 5, described by the expression (4), with, which occurs as a whole similarly to the processing presented above at the previous clock cycle, except for the third the input of the arithmetic unit 5 comes from the output of register 6 is not a zero value, and the value of g. Similarly, in accordance with expression (4), the samples of the sequence gi are calculated for all other values of i. Finally, as a result of performing the processing for the last k-ro count and getting it, we arrive at the initial

a state in which n first sequence values with a deformed spectrum are found in the first (left) bits of the shift register 2, and in the remaining m the counts of the input process. New computational iteration, etc. begins. until all counts of the input sequence arrive. The final processing result is read from the first (left) bits of shift register 2, and the frequency composition of this discrete process is changed from the initial one in accordance with the expression

  2 -arctg

and s in 9

1 - a-sinn

/AT,

S 21G t B 291; f

the frequency value in the source

 array;

f is the frequency value in the conversion array;

T is the interval between arrivals of samples on the input of the device.

Claims (1)

Invention Formula Phase filter containing the shift register, the first and second registers, and the output of the shift register is connected to the first input of the arithmetic unit, the second and third inputs of which are connected to the inputs corresponding to 022956 Respectively of the first and second registers, the output of the arithmetic unit is connected to the information input of the second register, and the arithmetic unit contains two adders and a multiplier whose output is connected to the first input of the first adder, whose output is the output of the arithmetic unit, the first, second respectively, the first input of the second adder, the second input of the first adder and the second input of the second adder, the output of which is connected to the first 15 input of the multiplier, the second input of which o is the input of setting the filter coefficients different / o accuracy, the first and the second multiplexers and the synchronizer are entered into it, the first, second, third, fourth and fifth outputs of which are connected respectively to the control input of the first multiplexer, clock the shift register input, the control input of the second multiplexer, the clock inputs of the first and second registers, the output of the first multiplexer connected to the information input of the shift register, the output of which is connected to the first information inputs of the first and second multiplexers, the second information inputs of which are connected to the output of the arithmetic unit, and the third information input of the first multiplexer is the information input of the filter. FIG. 2 ® F fuB.S