SU1196894A1 - Device for digital filtering - Google Patents

Abstract

A DEVICE FOR DIGITAL FSHTPLE 1, containing N multipliers, (N-1) adders and (N-1) registers, the output of the -th (i 1, N-1) register is connected to the first input of the -th adder, the second input of which connected to the output of the ((+1) multiplier, whose first input is

Description

The invention relates to computing and can be used in digital processing systems for radar, seismic, sonar, video and other signals. The purpose of the invention is to expand the functionality by performing a discrete Fourier transform. Figure 1 shows the structural diagram of the proposed device; Fig. 2 is a block diagram of the device operation in the calculation of the discrete Fourier transform. The device for digital filtering contains N multipliers 1. i (i 1, N), adders 2.i, registers 3.1, 4.1, AND 5 block of units, counter 6, clock generator 7, decoder 8. Counter 6 has a conversion factor equal to N. Registry 4 should receive information from two directions. The decoder 8 decrypts the zero M (N-1) state of the counter 6. Operation of the device when calculating the discrete Fourier transform. The device must calculate the trace of the following: N-1) (n) w; , (where x (n) are elements of the original sequence of length N i X (k) are elements of the transformed sequence; W is weight coefficients) We consider only the most common case where x (n) is a sequence of twofold numbers. Then the expression (1 ) can be rewritten in vvde ReX (K) Xx (n) RgW,) Zx (n). Obviously, the difference between the determination of the hyphenation (2) and (3) is 94 um only in the fact that in the calculation of (2) real parts will be fed to the second inputs of the multipliers 1, and in the calculation of (3) soft parts. The order of the input data and the weighting factors for expressions (2) and (3) is identical. Therefore, in the future, we will consider only expression (2), and for compactness of the record, consider X (k) and W to be real numbers. The second input of the multiplier 1.1 is the weighting factors V (multiplier 1.2 - multiplier 1.3; multiplier 1 .N) the block of elements And 5 and the enabling counting for the counter 6, It is assumed that the information in registers 3 and 4 is received on the falling edge of the synchronization signal .When describing the operation of the device, immediately take into account that. The input of the device is x (0) .The input of all multipliers 1 is W °. At the end of the clock cycle, the value of x (0) w is written to each register 3.i.The second input to the device input is x (1). W, multiplier 1.2 - W; multiplier 1.3 - W, multiplier 1.4 i multiplier 1.5 -Wj .In adder 2.1, form3 1. sum: x (1) V / j + x (0) W; adder 2.2 - (0) W; on adder 2.3 - x (1) / s -bxCOW on adder 2.4 - x (1) w | + x (0) W j on the adder 2.5 - x (1) (0) W.. In the third cycle, x (2) enters the device input. The input of the multiplier 1.1 is the W multiplier 1.2 -W |; multiplier 1.3 - W, multiplier 1.A - W |, multiplier 1.5Wy. On the adder 2.1, the sum is formed: x (2) wj + x (1) (0) W i on the adder 2.2 - x (2) А «у + х (1) + + x (0) W j on the adder 2.3 - х (2) xWr + xCi) Atf - «- xCOw i on the adder 2.4 - x (2) (1) w} + x (0) on the adder 2.5 - x (2) Wr + x (1) Wr + ( 0) W.

31

 in the fourth cycle, x (3) enters the input of the device. The input of the multiplier 1.1 is Wt; multiplier 1.2 -VJj; multiplier 1.3, multiplier 1.4 -W ° -, multiplier 1.5 -W. On the adder 2.1, the sum is formed: x (3) (2) Wj + xd) (0) W; on adder 2.2 x (3) WL + x (2) Wj + x (1) W / + x (0) W i on adder 2.3 - x (3) l + x (2) (1) Y / r + x (0) W j on the adder 2.4x (3) W + to (2) W −f − xd) (0) W;

Bt

on the adder 2.5 - x (3) W + x (2) W ++ x (l) wt-i-x (0) w.

In the fifth cycle, the input of the device is x (4). The input of the multiplier 1.1 comes Wy, the multiplier 1.2Wj; multiplier 1.3 - W, multiplier 1.4 - Wjv multiplier 1.5 - W. On the adder 2.1, the transformed sample X (4) x (4) Wy x x (3) i / | + x (2) w | + x (1) wj is formed + x (0) W; on adder 2.2 - converted X (3) x (4) (3) Wf «-x (2) (1) Wj + x (0) W i on supervisor 2.3 transformed X (2) x (4) w + + x (3) X / 5 + x (2) (1) w / + x (0) W i on the adder 2.4 - the converted sample X (1) x (4) (3) vQ3 + x (2) W5- + + x (1) V (/ i + x (0) W i on adder 2.5 transformed sample X (0) x (4) W + x (3) V (+ x (2) (1) w + x ( 0) w. The signal of the second output of the decoder 8 allows reception in registers 4 of information 1U1I received at their first information inputs.At the negative difference of the sync pulse received from the output of generator 7, at the end of the fifth cycle the registers 4.1–4.5 take values X (4 ) -X (0), respectively.

In the sixth (N + 1) clock cycle, a zero count of x (0) arrives at the device input. From the first output of the decoder 8, a signal to reset the registers 3 arrives. The inputs of the multipliers 1 receive the weight coefficients, as in the first cycle of the device operation. At the outputs of all adders, x40) N appears. The signal from the second output of the decoder 8 allows reception in the registers 4 of the information received at their second information input. At the end of the measure in pe96894 -

gister 4.2 is written X (4) to register 4.3 - X (3) i to register 4.4-X (2), to register 4.5-X (1).

In the seventh cycle, the input to the device, va, is received x (O. The inputs of multipliers 1 receive the same weights as in the second cycle, and the calculation of the converted samples of the new sequence, 0 x (k) continues. At the end of the cycle X (2) is accepted into register 4.5; X (3) i into register 4.3 - X (4) into register 4.4.

In the following, the calculations are repeated with a period of five cycles. In Figure 2, the following conventions are accepted: - resetting the .i registers 3iO |, - the result calculated on the i-M multiplier. -, the result calculated on the -th sum-Q re 2. i; the result calculated on the i-M adder 2.vk-m cycle; P4-5- to register 4. A number is taken that will not be used in computation; X (k) is the kth converted reference, Pth of the input sequence.

When implementing a digital filtering procedure, a device must compute an expression like

N-1 30

X ((K-n) h (t, C-V

where b (n) are the pulse coefficients

characteristics, x (i) - samples of the input signal.

When the device is operating in the digital filter mode, a logical zero signal is applied to the device start input, breaking the feedback between the output of the adder ZN and the input of the register 3.1. The same signal sets the counter 6 to the (N-l) -e state, thereby allowing reception

In registers 4 of the information received at their first information inputs.

The coefficient 1 (N – i) is continuously input to the input of the multiplier 1.i. Calculation is continuous. AT

Each cycle to the input of the device receives a new count of the input signal x (k). At the end of the kth cycle, register 4 is set to the value of the filtered sample X (k).

AND

Claims (1)

A DIGITAL FILTRATION DEVICE containing N multipliers, (N-1) adders and (N-1) registers, the output of the ί-th (ί = 1, Ν-1) register connected to the first input of the i-ro adder, the second input which is connected to the output of the (\ +1) th multiplier, the first input of which is (i + l) ~ b! M the input of the device coefficient, the second inputs of N multipliers are combined and are the information input of the device, and the first input of the first multiplier is the first input setting the device coefficient, the output j-ro (j = 1, N-2) of the adder is connected to the information input (j + Ι) reg Istra, characterized in that, in order to expand functionality by performing the Fourier transform, the Nth register, Nth adder, a group of H registers, a block of I elements, a decoder, a counter and a clock pulse are introduced into it it is connected to the synchronization input __ m ~ ro (t = 1, H) of the register, to the synchronization inputs of the group registers and to the counting input of the counter, the information output of which is connected to the decoder input, the first output of which is connected to the setup input of the tn-th register, the entries of the register reg PPs are connected to the second output of the decoder, while the output of the first multiplier is connected to the first input of the flth adder, the output of which is connected to the information input of the first register and the information input of the first register of the group, the second input of the Nth adder is connected to the output of N- register, the information = input of which is connected to the output of the AND block, the first input of which is connected to the installation input of the counter and is the device start input, the output of the ί-th (i = 1, N-1) adder is connected to the first information input (1 +1) th p group register, the output of the го-th (i = 1, N-1) group register is connected to the second information input of the (ί +1) -th group register, and the output of the M-th group register is the information output of the device, output (устройства-1 ) -th adder is connected to the second input of the block of elements I.