SU1377872A1 - Device for digital filtering - Google Patents

Abstract

The invention relates to computing and can be used in digital processing systems for seismic, radar video and other signals. The purpose of the invention is to simplify the device. The goal is achieved due to the fact that the device includes N (N is the filter order) input registers N multipliers 2, -2, N registers of coefficients 3, -3р4, N adders 4, -4 m, N blocks of registers 5, -5ts switch 6, synchronization unit, having synchronization outputs 8.1-.N, 9.1-9.N, 10.1-10.N, 11-14. 4 il. from $ / EOSffff SfBOK / JKO

Description

The invention relates to computing and can be used in digital processing systems for seismic, radar and other signals.

The aim of the invention is to simplify the device.

Fig, 1 shows a structural diagram of the device; FIG. 2 is a block diagram of a synchronization block; in fig. 3 is a sequence of control signals with digital filtering j in FIG. 4 - the same, when calculating the DFT.

The device for digital filtering (see, Fig. 1) contains N input registers 1.1 (1 1, N), N multipliers 2.1, N registers 3.1. Coefficients, N adders 4.1, N blocks 5.1 result registers, switch 6, block 7 synchronization, the outputs of the synchronization unit 8.1-8.N, 9; 1-9.N, 10.1- 10.N, 11-14.

In my output from the outputs 8.1-8.3 of the synchronization unit 7, are taken to registers 3.3, 3.2 and 3.1, respectively. Thereafter, the digital filtering procedure begins. Initially, in the registers of block 5.1 zeros are written. Switch 6 skips O to the second input of the adder 4.1.

0 At the end of the first clock cycle, the input sample x (0) is received from the signals from outputs 9.1 and 11 of the synchronization unit 7 to all input registers 1.1. In the second cycle at the outputs, cleverly5 inhabitants 2.1 will get the product

x (o) h (N-i), which, when folded with zeroes on adders 4.1, are written into blocks 5.1 of registers at the end of a clock. In block 5.3 of registers, the product x (0) h (0) is obtained, i.e. count X (0). In addition, at the end of the second clock cycle, registers 1.1 receive an input count X (1).

In the third clock cycle at the outputs of the Smartly Sync Block 7 (Fig. 2) of the residents 25, we get the product of the generator 15, the AND 16, x (1) h (ni) element, each of which is summable from the outputs 8.1-8.3 of the synchronization block 7, accepted in registers 3.3, 3.2 and 3.1, respectively. Thereafter, the digital filtering procedure begins. Initially, in the registers of block 5.1 zeros are written. Switch 6 skips O to the second input of the adder 4.1.

0 At the end of the first clock cycle, the input sample x (0) is received from the signals from outputs 9.1 and 11 of the synchronization unit 7 to all input registers 1.1. In the second cycle at the outputs, cleverly 5 inhabitants 2.1 will get the product

x (o) h (N-i), which, when folded with zeroes on adders 4.1, are written into blocks 5.1 of registers at the end of a clock. In block 5.3 of registers, the product x (0) h (0) is taken, i.e. count X (0). In addition, at the end of the second clock cycle, registers 1.1 receive an input count X (1).

In the third tact on the outs clever

a counter 17, a fixed memory node (ROM) 18, in which device control programs are stored.

Consider the operation of the device in the digital filter mode.

The device must calculate the expression of the form:

NI

X (k) x (k-n) h- (n), (1) p o

where h (n) - impulse coefficients

specifications;

x (1) - samples of the input signal. For simplicity, consider the case when N 3, i.e. The device must provide the following expressions:

X (0) x (0) .h (0);

X (1) x (1) -h (0) + x (0) -h (1);

X (2) x (2) -h (0) + x (1.) - h (T) + x (0) h (

It is conditional that the reception of information in all registers is carried out on the detected front of the clock.

Before directly implementing the digital filtering procedure, it is required to load the impulse response coefficients into the coefficient registers 3.1. To the input of the device coefficients input, h (0), h (1), h (2) are successively received, which, according to the clock pulses, feed

five

0

0

five

It works with the products obtained in the previous cycle and stored in blocks of 5.1 registers. At the end of the third clock cycle, in the register block 5.3, the sum X (1) h (0). + X (0) h (1) is received, i.e. X (1), in block 5.2 of registers, the sum x (1) h (l) + x (0) h (2) is taken. In addition, at the end of the third clock cycle, registers 1.1 are counted x (2).

In the fourth clock cycle at the outputs of the multipliers 2.1, we obtain the product x (2) h (Ni), each of which is summed on adders 4.1 with the results of the previous calculation cycle at the end of the 4th clock cycle. In block 5.3 of the registers x (2) h ( 0) + x (1) h (1) + + x (0) h (2) ,. those. countdown X (2).

At this point, the digital filtering procedure of the input array x (1) of length N ends. If it is necessary to process a new input sequence, the operation of the device is repeated, starting from the first clock cycle. Re-loading of the impulse response coefficients is performed only when they change.

Consider the operation of the device when performing a discrete Fourier transform (DFT). The reception of information in the registers is carried out on the falling edge of the sync pulse. Before performing the DFT, we load the weight coefficients Wo into the registers 3.1 coefficient 3

the factors: the coefficient W is loaded into register 3.2, the coefficient WJ is loaded into register 3.3, and so on. The coefficients are loaded only once.

The device must evaluate the following expression:

NI

I --JJ f)

X (k) .2lx (h) .W, О k: N-1, (2) n o

where x (n) are elements of the original sequence;

X (k) - elements of the transformed sequence;

W

kn

weights, WN e-J-lH, j FT,

KP (KP) "OAN

Since in the formula (2) the values x (p), X (k), W J are complex, all elements of the proposed device are designed to handle complex numbers.

The following calculations are required to obtain 6 output samples:

X (0) x (0) W ° + x (l) W ° + x (2) W ° + x (3) W ° +

rfx (4) W ° + x (5) W °;

X (1) x (0) W ° + x (1) (2) w | + x (3) W

+ x (4) (5)

X (2) x (0) W ° + x (1) W6 + x (2) (3) W6 +

+ x (4) (5) (3

X (3) x (0) W6 + x (1) (2) W ° + x (3) W6 +

+ x (4) W ° + x (5) W6 .;

X (4) x (0) W6 + x (1) (2) Wg + x (3) W ° +

+ x (4) (5) Wg;

X (5) x (0) Wg + x (1) (2) (3) W6 +

+ x (4) We + x (5) w ;.

Taking into account the symmetry of the weight coefficients W, it is sufficient to perform the multiplication by Wj, where i 0,1,2 ..., N / 2-1, and when calculating the sums 21x (n) Hn in accordance with formula (2) - subtraction, considering that W

 -W

kn4 NfZ

X (0) x (0) W ° + x (1) We + x (2) W ° + x (3) W2 + + x (4) (5) W

724

X (1) x (0) W6 + x (1) (2) (3) W ° +

+ x (4) (5) Wg; X (2) x (0) W ° + x (1) (2) (3) W ° +

+ x (4) w4x (5) wl; (4)

X (3) x (0) W6 + x (1) W ° + x (2) (3) W6 +

+ x (4) W ° + x (5) W °;

X (4) x (0) W ° + x (1) Wg + x (2) (3) W5 +

,,

+ x (4) W, + x (5)

X (5) x (0) (1) We + x (2) (3) W ° + + x (4) (5) Wg;

In the initial state, the zeros are written in blocks 5.1 of the result registers. Switch 6 skips O

to the second input of the adder 4.1.

In the first clock cycle, x (0) is input to the data input, which is taken to register 1.1 at the end of the clock cycle.

In the second cycle, at the output of the multiplier 2.1, we obtain the product x (0) W, which at the end of the cycle is received in the first register of the block 5.1 of the result registers.

In the third cycle at the output of the multiplier 2.1, we obtain the product x (0) Wg, which at the end of the cycle enters the second register of the block 5.1 of the result registers and the register 1.1. In addition, at the end of the third cycle in the register

1.2, count x (1) is accepted.

In the fourth cycle at the output of the multiplier 2.1 we get the product x (0) Wg, at the output of the multiplier 2.2 - the product x (1) U, at the output of the adder 4.2

the sum x (0) w ° + x (1) Wg, which at the end of the clock cycle is taken to the first register of the result registers block 5.2. The first register of block 5.1 is written x (0) W °.

In the FIFTH cycle at the output of the multiplier 2.1, we obtain the product x (1) Wg at the output of the multiplier 2.2 - the product of x (1) W, at the code of the adder 4.2 - the difference x (0) (1) W5, which is taken at the end of the second cycle register: block 5.2 of the result registers. In the second register block

5.1 is written x (0) W.B register

1.2 is adopted xCOW. Besides.

at the end of the fifth clock cycle, in register 1.3, a count x (2) is taken.

In the sixth cycle, at the output of the multiplier 2.1, we obtain the product x (0) Wg, at the output of the multiplier 2.2 - the product of xCDWfi, by the multiplier - 2.3, the product of x (2) W, at the output of the adder 4.2 - the sum x (0) W6 + + x (1) Wg, which at the end of the clock cycle is accepted into the first register of block 5.2, At the output of the adder 4.3 we get the sum x (0) W% x (1) (2) W /, which at the end of a clock cycle is received in the first register of the block 5.3, the first register of the block 5.1 enters x (0) W. . .

In the seventh bar on the output multiplied

tel 2.1 we get the product xCOW, the output of the multiplier 2.2 is the product of x (1) W, the output of the multiplier 2.3 is the product of x (2) W, the output

adder 4.2 - the difference x (0) x (1) Wg, which at the end of the clock enters the second register of block 5.3, At the output of the adder 4.3 we get the expression x (0) (1) wf + x (2) w |, which is taken to the second register of the block 5.3 at the end of a clock; x (1) W | is taken into register 1.2; W | is a register of 1.3 - x (2); register 1.1 enters the count x (3) and the output 12 of the synchronization unit 7 switches the switch 6 so that it passes the data to its second information input.

In the eighth cycle at the output of the multiplier 2.1, we obtain the product x (3) Wg, at the output of the multiplier 2.2 - the product of x (1) Wg, at the output of the multiplier 2.3 - the product of x (2) Wg, At the output of the adder 4, 1 get the expression

-2

This is accepted in the second register of block 5.1. At the output of the adder, we get the sum x (0-) W ° + x (1) W, at the end of the cycle the register is taken in the vt, block 5.2, At the output of su 4.3 we obtain the difference x (0) (2) Wg, which at the end of the cycle p is passed to the second register of the block

10 The register 1.1 accepts x (3) W the register 1.3 - x (2) Wg. In addition to the end of the ninth clock cycle, the count x (4) is taken into the register,

In the tenth step of the output mind

15 bodies 2.1 we obtain the product x at the output of the multiplier 2.2 - penetration x (4) Wg, at the output of the multiplier product x (2) W ,, At the output

ABOUT

Matrix 4.1, we obtain the expression x (20 + x (1) (2) W + x (3) W, which is taken as the first clock of the block p 5.1). At the output of the adder we get the expression x (0) Wg + x ( 1) Wg + x (2) W6-x (3) Wg-x (4) W, which is taken in the first p of the block 5.2 at the 25th clock cycle,

35

x (0) W ° + x (1) We + x (2) (3) W °, which is taken to the first register of the block 5.1 at the end of the clock cycle. At the output of the adder 4.2 we get the difference x (0) W ° - x (1) Wg, which at the end of the clock cycle is taken to the first register of the block 5.2, At the output of the adder 4.3, we get the expression x (0) (1) w | -x (2) W6, which at the end of the clock cycle is taken first register block 5.3.

In the ninth tact at the output of the multiplier 2.1, we get the product x (3) Wg, at the output of the multiplier 2.2 - the product x (1) And,

.., at the output of the adder 4.1 - the expression x (0) Wj-x (1) + x (2) (3) W6, which at the end is 45

50

thirty

adder we get the expression x (0) Wj-x (1) Wg + x (2) Wg, which at the end of the clock cycle goes to the first register of the block. In the eleventh clock cycle at output 2.1, we get the multiplier 2,

knife

x (3) Wg, output

the product x (4) Wg, at the output of the inhabitant 2,3 - the product x (2) w

output adder 4.1 we get you

x (0) W ° -x (1) w | -x (2) (3) W The second at the end of the clock cycle is taken up by the second register of block 5.1, On the adder 4.2 we get the expression 40 x (0) W ° -x (1,) (2) wf + x (3) Wg-x (4 which at the end of the clock cycle takes 5.2 into the second register, At the adder 4.3 we get the sum + x (1) (2) W °, which at the end of the second is accepted into the second register 5.3, B register 1.1 takes p (3) W, into register 1.2 - x (4) Wg, furthermore, at the end of the eleventh, register 1.3 taken off In the twelfth tact to exit 2.1, we get produced

2,

output multiplier 2, x (0) (1) W ° + x (2) (3) W ° product x (2) W

knife

х (3) Уб, at the output of the multiplier product x (4) W, at the output of inhabitant 2,3 - product x (5) W at the output of adder 4.1 we get you

 LVL 4 / VKg AV-J /

The last register of block 5.1 is taken at the end of the cycle. At adder 4.2 we get the expression

This is accepted into the second register of block 5.1. At the output of the adder 4.2 we get the sum x (0-) W ° + x (1) W, which at the end of the cycle is received into the second register, block 5.2, At the output of the adder 4 , 3, we obtain the difference x (0) (1) w - x (2) Wg, which is taken to the second register of the block 5.3 at the end of the clock cycle,

0 In register 1.1, x (3) Wg is accepted, in register 1.3 - x (2) Wg. In addition, at the end of the ninth clock cycle, in register 1.2, countdown x (4) is taken,

In the tenth cycle, at the output multiplied by 5 bodies 2.1, we obtain the product x (3) W, at the output of multiplier 2.2 - product x (4) Wg, at the output of multiplier 2.3 - product x (2) W ,, At the output sum OOO

Matora 4.1, we obtain the expression x (0) Bh + 0 + x (1) (2) W + x (3) W, which is taken to the first register of the block 5.1 at the end of the cycle. At the output of the adder 4.2 we get the expression x (0) Wg + x (1) Wg + + x (2) W6-x (3) Wg-x (4) W, which at the end of the cycle is entered into the first register of block 5.2, the output

0

adder 4.3 we get the expression x (0) Wj-x (1) Wg + + x (2) Wg, which at the end of the clock cycle is taken to the first register of the block 5.3, In the eleventh clock cycle at the output, we get 2.1 product of the multiplier 2.2 knife

x (3) Wg, output

five

five

0

the product of x (4) Wg, the output of the multiplier 2,3 is the product of x (2) wl, Ha

B

the output of the adder 4.1 we get the expression x (0) W ° -x (1) w | -x (2) (3) W, which is taken at the end of the clock in the second register of the block 5.1. At the output of the adder 4.2 we get the expression 0 x (0) W ° -x (1,) (2) wf + x (3) Wg-x (4) w, which is taken to the second register of the block 5.2 at the end of the clock cycle. At the output of the adder 4.3 we get the sum x (0) Wg + + x (1) (2) W °, which is taken to the second register of the block 5.3 at the end of the cycle, register p (3) W is taken to the register 1.1, 1.2 - x to the register 1.1 (4) Wg. In addition, at the end of the eleventh cycle, register 1.3 is counted x. (5) .. In the twelfth cycle, at the output of smart 2.1, we get the product

2.2 x 5 x (0) (1) W ° + x (2) (3) W °

knife

x (3) Ub, at the output of the multiplier product x (4) W, at the output of the multiplier 2,3 - product x (5) Wg, At the output of the adder 4,1 we get the expression of the LP 4 / VKg AV-J /,

The second one at the end of the clock cycle is taken to the first register of the block 5.1. At the output of the adder 4.2 we get

x (0) W ° + x (1) (2) w; + x (3) W ° + x (4) W,. which at the end of the clock cycle is accepted into the first register of block 5.2. At the output of the adder 4.3, we obtain the expression x (0) We + x (1) Wg + x (2) tf6-x (3) W ° -x (4) Wg + x (5) W | X (1), which at the end of the clock cycle is accepted into the first register of block 5.3.

In the thirteenth, so at the output of the multiplier 2.1 we obtain the product x (3) Wg, at the output of the multiplier 2.2 - the product jc (4) Wg, at the output of the multiplier 2.3 - the product x (5) W.

ten

at the end of the clock cycle, it is accepted into the first register of block 5.3.

In the seventeenth cycle on the multiplier 2.3, we obtain the product x (5) W. At the output of the adder 4.3 we get the sum x (0) (1) W ° + x (2) w; + fx (3) W ° + x (4) W ° + x (5) W ° X (0), which the end of the clock cycle is taken to the second register of block 3.3.

Further operation of the device is similar.

The synchronization unit 7 operates as follows. Upon receipt of the signal of the output of the adder 4.1, we get the sum of the 15th Start at the input of the AND 16 element with the x (0) W ° + x (1) (2) Wg + x (3) Wg, which is received at the end of the cycle register block 5.1. At the output of the M3 4.2, we obtain the expression x (0) (1) w | -x (2) W6-x (3) (4) W, which at the end of the clock cycle is taken to the second register of block 5.2. At the output of the adder 4.3, we obtain the expression x (0) W ° –x (1) w; + x (2) (3) W ° –x (4)

20

+ x (5) W4 X (4), which is at the end of a bar25

The clock 15 of the clock pulses through the element 16 is fed to the counting input of the counter 17, which starts the counting from zero, as the Start signal sets the counter 17 to zero. From the output of the counter 17 to the address inputs of the ROM 18, a sequence of command addresses is supplied to control the operation of the device. ROM 18 stores coefficient loading programs, digital filtering, and DFT calculations. The choice of the required program is carried out by supplying control signals to the address inputs of the ROM 30 18. Signal Mode provides a choice of filtering mode (single signal value) or DFT calculation mode (signal zero value). By applying a single signal to the input. Loading is performed by selecting a program that accepts filter coefficients or weights for the DFT in registers 3.1.

adopted in 5.3. In register

x (4) W

second register 1.2

block

6

accepted into register 1.3 - x (5) W,

6 In the fourteenth exit tact

: multiplier 2.2, we obtain the product x (4) Wg, at the output of multiplier 2.3 - the product x (5) W. At the output of the summator 4.2, we obtain the expression x (0) Wg − x (1) W ° + x (2) W ° −x (3) (4) W6, which is taken to the first register of block 5.2 at the end of the clock cycle. At the output of adder 4.3, we obtain the expression x- (0) Wg + + x (1) (2) (3) (4) w | -x (5) W6 X (2), which at the end of the clock cycle is taken to the first register of block 5.3 .

In the fifteenth cycle, at the output of the multiplier 2.2, we obtain the product x (4) Wg, and at the output of the multiplier 2.3 - the product x (5) W. At the output of the sum

Matrix 4.2, we obtain the sum x (0) + x (1) W ° + x (2) Wj + x (3) W ° + x (4) Wg, which is taken to the second register of block 5.2 at the end of the clock cycle. At the output of the adder 4.3, we obtain the expression x (0) Wg − x (1) w − x (2) w; −x (3) (4) wf + x (5) W x (5), which is taken at the end of a clock second register block 5.3. Register 1.3 accepts x (5) Wg. In the sixteenth cycle at the output of the multiplier 2.3, we obtain the product x (5) W5. At the output of the adder 4.3 we get the expression) W6 + x (2) x (3) Wg-x (4) W6-x (5) W6 X (3), which

at the end of the clock cycle, it is accepted into the first register of block 5.3.

In the seventeenth cycle on the multiplier 2.3, we obtain the product x (5) W. At the output of the adder 4.3 we get the sum x (0) (1) W ° + x (2) w; + fx (3) W ° + x (4) W ° + x (5) W ° X (0), which the end of the clock cycle is taken to the second register of block 3.3.

Further operation of the device is similar.

The synchronization unit 7 operates as follows. When a signal is received, the Start to the input of the element And 16 with

The clock 15 of the clock pulses through the element 16 is fed to the counting input of the counter 17, which starts the counting from zero, as the Start signal sets the counter 17 to zero. From the output of the counter 17 to the address inputs of the ROM 18, a sequence of command addresses is supplied to control the operation of the device. ROM 18 stores coefficient loading programs, digital filtering, and DFT calculations. The choice of the required program is carried out by supplying control signals to the address inputs of the ROM 18. Signal Mode provides a choice of filtering mode (single signal value) or DFT calculation mode (zero signal value). By applying a single signal to the input. Loading is performed by selecting a program that accepts filter coefficients or weights for the DFT in registers 3.1.

Claims (1)

Invention Formula A device for digital filtering containing N (N is the order of filing) input registers, N coefficient registers, N multipliers, N adders, N register blocks and a synchronization block, the i-th (i 1, N) output of the first group of which is connected to the clock input of the i-ro coefficient register, the output of which is connected to the first input of the i-ro multiplier, the output of which is connected to the first input of the i-ro adder, the output of which is connected to the information input of the i-ro block of registers, the i-th output of the second group of block synchronization is connected to the input enable input i-ro input register, the i-th output of the third the synchronization unit groups are connected to the i-ro synchronizer input of the adder, the first output of the synchronization unit is connected to the clock inputs of the register blocks and input registers, the second and third outputs of the synchronization unit are connected respectively to the receive enable inputs and output outputs of the register blocks, the i- output The input register ro is connected to the second input of the i-ro multiplier, the output of the j-ro (j 1, N-1) register block is connected to the second input of the (J + 1) th accumulator, and the output of the N-ro block of registers is an information output devices, information the ion input of which are interconnected first information inputs the coefficients of the device whose startup input is the synchronization unit startup input, characterized in that, in order to simplify the device, it contains a switch, the output of which is connected to the second input of the first adder, the output of the N-ro block of registers is connected to the new information input of the switch, the second the information input of which is the input of the setting of the logical zero of the device, the input of the setting of the loading mode of coefficients and the input from which the setting of the calculation mode of the computation mode are the first and second inputs The settings of the synchronization unit mode, the fourth output of which is connected to the control input of the commodity registers, the information inputs of the tator, and the output i-ro (i - 1, N) multiplied by the registers of coefficients are connected to the bodies connected to the second information one and are the input to the input i-ro input register. Phie. 2 the coefficients of the device whose startup input is the synchronization unit startup input, characterized in that, in order to simplify the device, it contains a switch, the output of which is connected to the second input of the first adder, the output of the N-ro block of registers is connected to the first information input of the switch, the second the information input of which is the input of the setting of the logical zero of the device, the input of the setting of the loading mode of the coefficients and the input of the setting of the computing mode of which are the first and second in the steps of setting the mode of the synchronization unit, the fourth output of which is connected to the control input of the comm5 .7 P FIG. J