SU1571611A1 - Device for calculating of fast fourier transform - Google Patents

Abstract

The invention relates to digital computing and can be used in digital signal processing systems. The purpose of the invention is to simplify the device. This is achieved due to the fact that the device includes a clock pulse generator, a counter, four blocks of permanent memory, a multiplier unit, two blocks of buffer memory, two groups of A (A is a prime number) computing blocks of the first type, each of which contains a buffer register, result register, adder and trigger, two groups from B / B - a prime number

^A. B = N is the size of the transformation / computational blocks of the second type. Each of them contains a switch, a trigger, an adder, and two groups of A buffer registers. 8 il.

Description

The invention relates to digital computing, is intended to compute a fast Fourier transform and can be used in digital signal processing systems.

The aim of the invention is to simplify the device by reducing hardware costs.

FIG. 1 through 8 are a block diagram of a device for computing a fast Fourier transform.

The device (Figs. 1-8) contains information input 1, block 2 of buffer memory, 3 clock pulse generator, counter (modulo M) 4, block 5 of permanent memory, second common information bus 6, sync bus 7, block 8 permanent memory, the first group of computational

blocks of the first type 9.p (, A), each of which consists of an adder 10.p, a register (result) 11.p, a buffer register 12.p, a trigger 13.p, the first common information bus 14, a group of computational blocks 15 .р (, В), each of which consists of trigger 1б.р, switch 17.р, groups of buffer registers 18.р, k (, A), adder 19, р, group b of uferny registers 20.pk (, A), constant memory unit 21, multiplication unit 22, third common information bus 23, third group of second type computational blocks 24.p (, B), each of which consists of trigger 25.p, switch 26.p , groups of buffer registers 27.pk (, A), adder 28.p, groups of buffer registers 29.pk (, A),

en j

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the fourth common information bus 30, a group of subtractive blocks of the first type 31.p (, A), each of which consists of adder 32, p „register (result) 33.p, buffer register 34.p, trigger 35.p, outputs 36.p (, 4) of block 5 of permanent memory, two-bit outputs 37.p (p-1, 2x (A + B)) of block 8 of permanent memory, block 38 of buffer memory, information output 39 of the entire device , fixed memory unit 40, outputs 40 - 41.p (, 2B) of the fixed memory unit.

The device calculates the fast Fourier transform according to the Winograd algorithm with a period of C readings, where xB (A and B are prime numbers).

Consider the operation of the device to the point. When describing the operation of the device, the following abbreviations are used: See - adder, Tr - trigger, Pr - register, GDP - buffer memory block, ROM (numbered output) - permanent memory block, Mind - multiplier. To be specific, we take,, and the conversion period will be 15, a number. Square-wave square-wave pulses come from the generator. We will assume that the triggers, registers in all computing elements are triggered by the leading edge of the clock signal (positive differential). We omit the first 15 work cycles for counting, since during this time the input counts X (p) (, 15) come in direct sequence from input 1 to BBU 2. After that, three pause cycles follow, since counter 4 works modulo. From the next clock cycle, the input samples X (p) in the sequence we need go to the first common information bus.

1 tact. BBP 25 X (0).

2pcs. BBP (5); Pr 12. (Q);

ROM 5 (36.1) See 10.1 X (0).

l

BBP (10); ROM 5 (36.1) F

Pr 12. (0); See 10.1-0; Tr 13. Wg 12.2 “X (5); See 10. (0) + X (5); Pr 11.1 X (0).

BBP (3); See 10.

Pr 12. (0); Pr 11. Tr 13. Pr 12.2-X (5); See 10. (5); Pr 11. (0) + + X (5); Tr 13. Wg 12.3 X (10); See (0) + X (5) + + X (10).

-, to

- | | five

20 25 jq jj to

45

.

50

55

5takt. BBP (8); Pr 12. (3);

Pr 11. ROM 5 (36.1) G; See 10.1-X (3); Pr 12.); See 10. (5); Pr 11.2-X (5); Tr 13. Prg 12. (10); See Y. (5) + X (10); Pr 11.3 (Y (1)) X (0) + X (5) + X (10)).

6takt. BBP (13); Pr 12. (3);

Pr 11.1-X (3); ROM 5 (36.1) Tr 13. See 10. Prog 12. (8); See 10. (3) + + X (8); Pr 11. (5); Pr 12.3 X (10); See 10. (5) -X (10); Pr 11.3 (Y (2) X (5) + X (10)).

7tact. BBP (6); Pr 12. (3);

Pr 11.1-0; See 10. Pr 12.2 X (8); See 10. (8); Pr 11.2 X (3) + X (8); Tr 13. Tr 13. Pr 12. (13); See 10.3-X (3) X (8) + X (13); Pr 11.3 (Y (3) X (5) -X (10). Next, the work of the group of computing blocks 9 continues according to the described algorithm. The control signals arrive at the adders of the computing blocks 9 so that at the output of the first group we get the result equivalent to multiplication two matrices (summation in parentheses in the second matrix occurs modulo 15):

1 1 P Gh (p) 1

About 1 1 x X (p + 5) LO 1 1J Lx (p + 10) J where X (p) is the input signal samples, 3,6,9,12.

We will consider the work of the group of computing blocks 15.p, starting with the 5th cycle.

5takt. Prg 11. (1) (this value and

all subsequent ones arrive at the second common information bus 6 for the group of computing blocks 15, therefore, in the future, instead of the sign Pr 11.3, it will be 111 6, which means bus 6); ROM 5 (36.2) (with 1 on the control input, the switches 17.p of group 15 (reference designation K 1.p) transmit information from the first inputs; To 17. (See 19.1 -Y (1).

6takt. ROM 5 (36.2) G; 111 (2b

K 17. (2); Pr 18.1. (1); See 19. (2); Pr 20.1. (1).

7tact. ROM 5 (36.2) 111 (3);

K 17. (3); Pr 18.1. (2); Pr 18.1. (1); See 19.1-t (3);

5157161

Pr 20.1. (2); Pr 20.1.2 -Y (1).

tact. ROM 5 (36.2) ROM 40

(41.1) D; Tr 16. See 19. Pr 20.1. (3); Pr 20.1. (2); Pr 20.1.3 Y (1); K 17.2-7 (4); See 19.2 Y (1) + Y (4).

tact. Tr 16. See 19. u

Pr 20.1. Pr 20.1. (3); Pr 20.1. (2); K 17. (5); Pr 20.2. (1) + Y (4); See 19.2 Y (2) + Y (5); Pr 18.2. (4).

0tact Tr 16. Prg 20.1. ,five

Pr 20.1, (3); K 17. (6); Pr 20.2. (2) + Y (5); Pr 20.2. (1) + Y (4); See 19.2 Y (3) + Y (6); Pr 18.2. (5); Pr 18.2. (4) .20

1 tact. Tr 16. ROM 40 (41.r / r

 1.5 /) Tp 16. Wg 20.1. K 17.2-7 (4); Pr 20.2. (3) + Y (6); Pr 20.2. (2) + Y (5); Pr 20.2.3 25 Y (1) + Y (4); See 19.2-7 (4); Pr 18.2.1-7 (6); Pr 18.2.2 7 (5); Pr 18.2. (4); K 17. (7); See 19. (1) +7 (4) + +7 (7). .thirty

2pcs. Pr 20.1. K 17. (5);

WG 20.2. (4) j WG 20.2.2 7 (3) +7 (6); Pr 2Q.2. (2) + 7 (5); See 19.2-7 (5); Pr 18.2. (4); Pr 18.2.2-7 (6); Pr 18.2. (5); K 17.3-7 (8); 3 Pr 18.3. (7); CM 1. (2) + + Y (5) + Y (3); Pr 20.3. (0 + + Y (4) + Y (7); Tr 1b ..

3takt. Tr 1b. Pr 20.1. 4Q

K 17.2-7 (6); Pr 20.2. (5); Pr 20.2. (4); WG 20.2.3 7 (3) +7 (6); See 19. (6); Pr 18.2. (5); Pr 18.2.2 7 (4); Pr 18.2. (6); K., 17. (9); Pr 18.3. (8); Pr 18.3.2-7 (7); See 19.3 713) +7 (6) +7 (9); Pr 20.3.1 -Y (2j + Y (5) + Y (8) j Pr 20.3.2 7 (1) +7 (4) +7 (7) .50

4tact rom 40 (41., 5 /)

Tr 16, Tr 16,

K 17. (4); Pr 20.1.

Pr 20.2. (6); WG 20.2.2

7 (5); Pr 20.2. (4); See “19.7.2-7 (4); Pr 18.2.1-7 (6); Pr 18.2.2-7 (5); Pr 18.3.2 7 (8); Pr 18.2. (4); K 17.3-7 (7); Pr 18.3. (9);

Pr 18.3.3-7 (7); See 19.3 —Y (4) + Y (7); Pr 20.3. (3) + 7 (6) +7 (9); Pr 20.3. (2) + 7 (5) + Y (8); Pr 20.3.3-7 (1) + 7 (4) + Y (7); K 17.4-7 (10); See 19. (1) + Y (4) + Y (7) + T (10).

5takt. Tr 16, Pr 20.1.

K 17. (5); Pr 18.2. (4); Pr 18.2.2-7 (6); Pr 18.2.3 -7 (5); See 19. (5); Pr. 20.2. (4); Pr 20.2. (6); Pr 20.2. (5); K 17.3-7 (8); Pr 18.3. (7); Pr 18.3.2 Y (9); Pr 18.3. (8); See 19. (5) + Y (8); Pr 20.3.1 7 (4) + Y (7); Pr 20.3. (3) + + Y (6) + Y (9); Pr 20.3. (2) + + Y (5) + Y (8); K 17.4-7 (11); Pr 18.4. (10); See 19.4 -Y (2) +7 (5) +7 (8) +7 (11); Pr 20.4. (1) +7 (4) +7 (7) +7 (10).

6takt. Tr 16. Prg 20.1.

K 17.2-7 (6); Pr 18.2. (5); Pr 18.2.2-7 (4); Pr 18.2.3 7 (6); See (6); Pr 20. (5); Pr 20.2. (4); Pr 20.2. (6); K 17. (9); Pr 18.3. (8); Pr 18.3.2 -7 (7); Pr 18.3.3-7 (9); See 19.3-7 (6) +7 (9); Pr.20.3.1- -7 (5) +7 (8); Pr 20.3. (4) + + Y (7); Pr 20.3. (3) + Y (6) + +7 (9); K 17. (12); Pr 18. (11); Pr 18.4. (10); See 19. (3) + Y (6) + Y (9) + Y (12); Pr 20.4. (2) + Y (5) + Y (8) + +7 (11); Pr 20.4. (1) + Y (4) + +7 (7) +7 (10).

7tact. ROM 4.0 (41. P / p-1, 5 /) G;

Tr 16. Tr 1b, Pr 20.1. K 17.2-7 (4); Pr 18.2. (6); Pr 18.2.2 -7 (5); Pr 18.2. (4); See 19. (4); Pr 20.2. (6); Pr 20.2. (5); Pr 20.2.3 7 (4); See 19.3-7 (4) -7 (7); K 17.3-7 (7); Pr 18.3.1-7 (9); Pr 18.3.2-7 (7); Pr 20.3.1 7 (6) + U (9); Pr 20.3. (5) + 7 (8); Pr 2Q.3. (4) + Y (7); K 17.4-7 (10); Pr 18.4.1 -7 (12); Pr 18.4. (11); Pr 18.4. (10); Refer to 19.4 Y (4) + Y (7) + Y (10) ;. Pr 20.4.1 Y (3) + Y (6) + Y (9) + Y (12); Pr 20.4. (2) + Y (5) + Y (8) + Y (11); Pr 20.4.3-7 (1) +7 (4) +7 (7) + +7 (10); K 17. (13); Cm

19.5 "Y (1) + Y (4) -i-Y (7) + Y (10) + + Y (13).

8tact. Tp 16, Pr 20.1.

K 17. (5); Pr 1802. (4); Pr 18. 2. (6) 5 Pr 18.2,3); See 19.2 “Y (5); Pr 20.2.1-Y (4); Pr 20.2. (6); Pr 20.2. (5) j c 17. (8); Pr 18.3.); Pr 18.3.2 Y (9); Pr 18.3. (8); See 19. (5) -Y (8); Pr 20.3.1 Y (4) -Y (7) j Pr 20.3. (6) + + Y (9); Pr 20.3.3-Y (5) + Y (8); K 17. (11); Pr 18.4.1 (10); Pr 18.4.2 Y (12); Pr 18.4. (11); See 19.4 Y (5) + Y (8) + Y (11); Pr 20.4.1 Y (4) + Y (7) + Y (10); Pr 20.4.2 -Y (3) + Y (6) + Y (9) + Y (12) S Pr - 20.4. (2) + Y (5) + Y (8) -fY (11); K 17. (14); Pr 18.5.1 Y (13); Y (2) + Y (5) + Y (8) + Y (11) + + Y (14) CM 19.5,

9takt. Tp 16. Pr 20.1,

Pr 18.2. (5); Pr 18.2.2 —Y (4); Pr 18.2. (6); K 17. (6); CM 19. (6); Pr1 20.2. (5); Pr 20.2.2 Y (4); Pr 20.2. (6); K 17. (9); Pr 18.3. (8); Pr 18.3. (7); Pr 18.3.3 Y (9); CM 19. (6) -Y (9); Pr 20.3. (5) -Y (8); Pr 20.3. (4) -Y (7); Pr 20.3.3 Y (6) + Y (9); K 17. (12); Pr 18.4. (11); Pr 18.4.2 Y (10); Pr 18.4. (12); Pr 18.4. (11) i Pr 18.4.2 Y (10); Pr 18.4. (12); CM 19. (6) + Y (9) + Y (12); Pr 20.4. (5) + Y (8) + Y (11); Pr 20.4. (4) + Y (7) + Y (10); Pr 20.4. (3) + Y (6) + Y (9) + + Y (12); K 17. (15); Pr 18.5. (14); Pr 18.5.2 Y (13); CM 19. (3) -fY (6) + + Y (9) + Y (12) + Y (15). Then the work of the group of computing blocks 15.p is continued by the opian algorithm. The control signals on the adders 19.p come in such a way that at the output of group 15 we get a result equivalent to the deceleration of the matrices:

; ; ; one ; ) +

3 5 10

15

20

25

thirty

35

40

45

50

55

18

where Y (p) is the values arriving at the common information bus 6 (p-1,6,11).

From the information output of the computing unit, 15.5 values are fed to the input of the multiplication unit 22, to the other input of which 21 values of weighting coefficients and attributes are received from the ROM. After multiplying in block 22, the multiplications of the value go to the third common information bus 23.

The group of computing elements 24.p works similarly to the group of computing blocks 15.p (, 5). The control signals to the adders 28.p act in such a way that the output will be the values that would be obtained by multiplying the two matrices:

 Y (p) Y (p + 1) Y (p + 2) Y (p + 3) Y (p + 4) LY (p + 5)

where Y (p) is the values arriving at the third common information bus 23 (, 7.13). From the information output of the computing unit 24.5, the values are fed to the fourth common information bus 30,

The group of computing blocks S1.p (, 3) works similarly to the group of computing blocks 9.p for which the algorithm is described above. The control signals arrive at the adders 32.p in such a way that, at the output of the computational blocks, we obtain the values that would be obtained by multiplying the two matrices:

 X (k) x (k + 1) Lx (k + 2)

where X (k) is the values arriving at

fourth common information bus 30 (, 4.7, 10.13).

The information output 31 of the third computing unit receives the values at the input of the buffer memory unit 38, which outputs the values in the order in which they are received at the input of the first buffer storage unit 2.

Claims (1)

Invention Formula A device for calculating a fast Fourier transform comprising t-clock pulse generator and the first group of A (L is a prime number) computing blocks of the first type, the information output of the 1st (, A-1) computing block of the first type of group being connected to the first information input of the (1 + 1) -th computing block the first type of group, the first synchronization input of which is connected to the synchronization output of the 1st computational unit of the first type of group, while the computational unit of the first type of group contains an adder, a trigger, a result register and a buffer register whose output is connected to The first information input of the adder, the second information input of which is the first information input of the computing unit of the first type, the second information input of which is the information input of the buffer register, the clock input of which is connected to the clock input of the trigger of the first type , the second synchronization input of which is the synchronizer input of the adder, the output of which is connected to the information input of the result register, the output of which This is an information output of a computational unit of the first type, characterized in that, for the sake of simplicity, it contains a counter, two blocks of buffer memory, four blocks of permanent memory, a multiplication unit, a second group of A computation blocks of the first type, the first and second groups of B (B is a simple number; - the size of the conversion) computing blocks of the second type, and the information output of the j-th (, B-1) computing block of the second type of group is connected to the first information input of the (j + +1) th computing block of the second type, the first synchronization input of which is connected to the output synchronization j-ro computing unit of the second type of group, while the output of the clock pulse generator is connected to the counter input of the counter, the information output of which is connected to the address inputs of the first, second, third and fourth blocks of constant the first and fourth blocks of the buffer memory; the outputs from the first to the fourth of the first block of permanent memory are connected to the first synchronization inputs, respectively, of the first computing unit of the first type of the first group, the first computing blocks of the second type of the first and second groups, and the first computing unit block of the first type of the second group, K-th (, A) the output of the second block of permanent memory is connected to the second synchronization input of the K-th computing block of the first type of the first group, (K + A) -th and (K + A + B) outputs of the second block these memories are connected to the second synchronization inputs of Kx computing blocks of the second type, respectively, of the first and second groups, and (K + A + 2B), the second output of the second permanent memory block is connected to the second synchronization input of the Kth computing block of the first type the second group, the 1st and (1 + B) -n (the outputs of the third constant block are connected to the third synchronization inputs of the 1st computing blocks of the second type of the first and second groups, the output of the fourth constant memory block is connected to the first input of the multiplier, the output to expensively connected to the second information input (K-th computing block of the second type of the second group, the output of the B-th computing block of the second type of which is connected to the second information input of the 1st computing block of the first type of the second group, output of the A-th computing block of the first type connected to the information input of the first block of the buffer memory, the output of which is the information output of the device, the information input of which is the information input of the second block of the buffer memory, output to second is connected to the second information input of the 1st computing unit of the first type of the first group, the information output of the A-th computing unit of the first type of which is connected to the second information input of the K-th computing unit of the second type of the first group, information output of the B-th computing unit of the second type which is connected to the second input of the multiplication unit, and the computing unit of the second type of group contains a trigger, a switch, an adder, the first; the second group of A serially connected buffer G / W. rtl 372 & 0) 37.1 - Fi & .1 I p ± sh W.A tg 1440 ± 19.1 P.1 36.2 PA L 6 - 41.2B J FIG. 2 4 / .1 15.1 20.1.1 20J.A 18.1L W.K ABOUT , //. 16L J gJ // J7 / fs / R P8 i 37.A + B + 1 28.1 26L N / a1 36.3 22 23  ( } 58 m Y.1 -.... 2 Fiel . i 2S1A 24.1 ....-ъШ.А about one 41.8 + 1 25L Zt Fig 5 U WITH . Z7 --J Rig. b l /) J7f 37. A + 28 28.8 J / 7 - - . ea gtllr J l / L / 35.1 thirty - 37.2CA + 8) qbe.8