RU1809441C - Multichannel priority device - Google Patents

Abstract

The invention relates to computer technology and can be used to provide priority access to the device. The purpose of the invention is to increase the speed of the device by excluding from the survey channels that do not have service requests. A group of AND elements has been introduced into the device, and decoders, blocks of I. elements, 2 ill.

Description

The invention relates to the field of computer technology and can be used to provide priority access to a shared device.

The purpose of the invention is to improve performance by eliminating channels without service requests from the survey.

Figure 1 shows a structural diagram of a device; Fig. 2 is a structural diagram of a high-order select block (BSSR).

The device contains (FIG. 1) an OR-NOT element 1. AND element 2, an OR element 3, a pulse shaper 4, a delay element 5, a group of OR elements 6, a high-order bit selection block 7 containing (FIG. 2) AND elements 8 with direct and inverse inputs, channels 9. each of which contains a trigger 10, an OR element 11, a second, first group of And 12, 13. elements 14, a decoder 15, a channel response 16 output, a channel reset input 17, a group of code inputs 18 devices, input 19 channel request.

The device operates as follows.

In the initial state, the registers 14 and the triggers 10 are in the zero state, therefore, using the OR-NOT 1 element, the And 2 element is opened. At random times from the subscribers (not shown) to the request inputs 19 of the corresponding channel 9, request signals; as a logical unit. At the same time, the priority codes are received from the subscribers to the corresponding groups of code inputs of the device 18 (the higher the priority, the higher the code). The device uses a binary priority code. The subscribers do not have the same codes. If there is no request from the subscriber, then the code does not arrive at the group of code inputs of device 18, because the code will be zero. The request signal, passed through the element OR 3 and the open element AND 2, generates a pulse along the leading edge with the help of a pulse shaper 4, through which the priority codes are entered into the registers 14 of channel 9 through the first group of elements And 13. In accordance with the received code, a signal appears at the corresponding K-th (K 1, H) output of the decoder 15

(L

with

00

about

H)

-

logical unit. This signal opens at the first input the Kth element AND of the second group of elements AND 12 of its channel, and, passing through the Kth element OR of the group of elements OR b, it enters the high-order selection block 7 (the BSSR circuit is shown in figure 2) . At the output of this block. Which corresponds to the largest priority code from the received, a signal occurs.

Suppose that the high-order bit corresponds to the K-th signal of the decoder 15 of channel 9. Then, from the K-ro of the output of the BSSR 7, the signal of the logical unit goes to all K-th elements AND of the second group of elements And 12 of all channels 9. Then, after a delay time equal to the operation of the register 14, the decoder 15, the group of elements OR 6 and BSSR 7, from the output of the delay element 5 of the device, the pulse previously generated on the former 5 is displayed. This pulse constructs all the And elements of the second group of elements And 12 of all channels 9. As a result, at the output of the Kth element of the second group of elements And 12 of channel 9, corresponding to the Kth (oldest available) priority code, a single signal is generated, which Having passed through the OR element 11 of its channel 9, it will set the trigger 10 to a single state. Thus, at the output of the response 16 of channel 9 corresponding to the senior priority code, a single signal is generated, indicating the resolution of capture of the common trunk. As this signal is generated using the OR-NOT 1 device element, the -AND element 2 of the device is closed. After completion of the exchange of information between subscribers through a common trunk, a single signal is received at the reset input 17 of the channel. This signal is used to reset trigger 10 and channel register 14. As a result, the And 2 element opens again and a further selection of the channel with the highest priority code 1 occurs from the channels that have submitted exchange requests. Subsequently, the operation of the device is repeated. The selection of a high order is performed as follows. When signals are received at the inputs of the BSSR 7 signal ,, -. corresponding to the senior digit (the older the digit, the higher the input sequence number of the BSSR 7), closes all the AND elements 8 of the BSSR 7, the sequence number of which is less than the input number of this signal.

After that, this signal corresponding to the high order bit arrives at the corresponding output of the BSSR 7.

Claims (1)

The claims A multi-channel priority device containing an OR-NONE element AND, element И И, pulse generator, delay element, group of OR elements, channels, each of which contains a register, trigger, group of AND elements, single output of each channel trigger is a response output of the device and is connected to the corresponding input of the OR-NOT element, the output of which is connected to the first input of the AND element, the second input of which is connected to the output of the OR element, the group of inputs of which is the group of request inputs of the device, the output of the element And is connected to the input of the pulse shaper, especially because in order to increase the speed of the device, a group of (H- 1) -ro (H- i number of requests) of AND elements. And in each channel - a decoder, a block of AND elements and an OR element, the group of code inputs of the device is connected to the group of inputs of the block elements of the channel And, the output of the pulse former is connected to the input of the delay element, with the inputs of the blocks of elements And channels, the group of outputs of the block of elements And of each channel is connected to the group of information inputs of the register of its channel, the group of outputs of which is connected to the group of inputs of the channel decoder, K (, Н), the output of which is connected to the first input of the Kth element AND of the group of its channel and with the channel of the same name, the input of the Kth element AND of the I. group, the output of the Kth element AND of the channel group is connected to the Kth input of the OR element of the channel, the output of which is connected to the single input of the channel trigger, the channel trigger zero input is a channel reset input and is connected to the channel zeroing input, the delay element output is connected to the second inputs of the AND elements of all channels, the output of the first OR group element is connected to the direct input of the first AND element, output 2, ... , (Н-1) of an OR element of the group is connected to the direct input of the i-ro of the And element of the group and with the corresponding inverse inputs from the first to (H-2) th elements of the AND group, the output of the Hth element of the OR group is connected to the first inverse inputs of all the elements of the And group and to the third inputs of the H-elements AND of the group of all channels, the output of the 1st t ...., (H-1) j element AND groups is connected to the third inputs of j-x elements AND groups of all channels.,