SU813421A1 - Device for realization of walder algorithm - Google Patents

Description

The invention relates to a computing technique and can be used to calculate elementary functions displayed using Wolder iterative algorithms. Devices for computing elementary functions are known that implement Walder algorithms, which contain combination combiners, subtractors, registers, memory and control and synchronization nodes i and 2. The closest analogue is a device for implementing the Walder algorithm, containing memory tt control units, gigabyte adders, shift nodes, registers and switches p. The disadvantage of this device is the complex structure due to the non-uniformity of the nodes included in it and the need for synchronization to implement the multi-cycle computing process. The calculation time (T) in such a device is determined not only by the time of the summation cycle (t), but also by the loss of time for sending the results of each summation cycle to the corresponding registers and memory access (1c), i.e. (Vtn), where n - kolkkshestao steps (iterations). The purpose of the invention is to punch & 1 action in the homogeneity of the structure of the device. In order to achieve this goal, the device is built in the form of n sequentially connected iteration blocks, each of which contains three totalizers and a switch, while the control inputs of the BETT accumulators of each iteration unit are connected to the output of the switch, the outputs of the first and second adders block (1, ..., p -1) are connected to the first inputs, s.respective of the first and second adders-subtractors of the (i +1) -th iteration block directly, and with the second inputs of the corresponding But the second and first summators of the (i + 1) -th iteration block are shifted by i bits, the first inputs of the first and second subtractors of the first Iradio block are connected respectively with the first and second, and the second inputs respectively

the second and first information inputs of the device, the first input of the third adder-recipient of the first iteration block is connected to the third information input of the device, the output of the third adder-subtractor of each i -th iteration block is connected to the first input of the third adder-read out (-i + 1) - go iterative. The outputs, signs of the bits of the second and third adders-subtractors of each i -th iteration block are connected to the information inputs of the switch () -ro of the iteration block, the control input of the switch of each j -th iteration block {j 1 ,,. , p) is connected to the control bus of the devices the second input of the third adder-sub-j of the j -th iteration block is connected to the corresponding input of the device constant, the inputs of the switch of the first v testing block are connected to the sign inputs of the device, the outputs of the adders- ychytateley n -th iteration unit with the information device outputs.

The drawing shows a diagram of a device for implementing a Wolder algorithm.

The device contains n iteration Hbtx. blocks 1 (1, 1 ,,, .., l), each of which has inputs 2-8 and outputs 9-13. Each iteration unit 1 includes summators-read 14-15 and switch 17, inputs 2 All units 1 are connected to the control bus 18 of the device.

The inputs 3 and 4 of each j th iterative block 13 are supplied with the values of Y- and SicrnYj (inputs 3 and 4 of the first iteration block 1-, to which the values of s-intr - are connected to the sign inputs of the device, and the inputs 3 n 4 of all subsequent iteration blocks 1 are connected to outputs 9 and 10, respectively, of the previous iteration blocks 1). From inputs 3 and 4 of each block 1 value; . and Chz arrive at the information inputs of the switch 17 of this block 1 At the inputs 5-7 of each if block, the values Xj, 4.J and H are received, (inputs 57 of block 1, the initial values X, and 4L arrive at;); in:;: with the device, and inputs 5-7 of all subsequent iteration blocks 1 are connected to outputs 11-13, respectively, of the previous iteration blocks 1). Input 7 of each block 1 j, to which the constant value arc-ts l is applied, is connected to the corresponding input of the device constant. Outputs 11-13 of each block 1-J, on which

+ 1 and 4j- +1 are Xj +1, Y

dinene with outputs of totalizer adders 14-16 included in this block 1, and outputs 9 and 10 (on the coils, Sifl values of N +1 and +1 are formed) with outputs of significant digits of subtractors 14 and 15. Outputs 1113 unit 1. connected to the information outputs of the device.

Consider the operation of the device on the example of the number of trigonometric functions sin sin and 0054

The computational process is determined by the system of iterative equations W. .. FSC, oirctcg;

...

lX., -, - Xj 5icjn4.,,. (lj where 1 - 1,2,.,., v.

The initial conditions for the j -th iteration block 1j for calculating the (3 + 1) -th process step (1) is $ potts: at input 1, a signal that passes a signal to the KOMMyTaTqaa 17 signal ./; ca inlet 5 -

Claims (2)

1. QCCP copyright certificate No. 546890, cl. GI 06 F 15/34, 1973. 2. USSR author's certificate No. 519717, cl. q 06 P 15/34, 1974. . w Sijn xj s 1G yj 12 J VI / J Jl grcf y / f n 3 ZHG 9 G7G 12 n 7 13 / J -X