SU564638A1 - Device for solving linear algebraic equations systems - Google Patents

Description

(54) DEVICE FOR SOLVING SYSTEMS OF LINEAR ALGEBRAIC EQUATIONS

one

The invention relates to the field of computer technology and can be used in the construction of specialized and probe-oriented calculations.

devices and machines.

A device for simulating & 1 alternating differential equations is known, comprising a digital unit, analog memory mapping devices, two summing amplifiers with digital controllable impedances in the input circuits, and keys 11. This device can be used to solve systems of linear algebraic equations that are preliminarily reduced to an equivalent system of linear differential equations.

The low accuracy of solving such a device is due to the limited accuracy of analog blocks, and the long time to solve systems of algebraic equations is due to the inertia of integrators necessary to ensure the stability of the solution process. The closest technical solution to the invention is a device for solving systems of linear algebraic equations.

neny, containing groups of increment adders, increment registers, units of increments of increments, adder, a group of inputs of which are connected to the outputs of nodes of multiplication of increments of a group, the first inputs of which are connected to the outputs of the corresponding increment registers of the group, whose inputs are connected to the inputs of the corresponding totalizer adders of the group whose outputs connected to the outputs of the device 2.

The disadvantage of this device is a large amount of equipment, because when solving the system of equations and the -th order, the device uses (n + M) multiplication units of increments, n integrators, and AND adders ka () of inputs, a large solution time due to inertia, introduced by integrators, which limits the possibility of using the device in real-time control systems; the difficulty of automating input to the device and because of the large number of multiplications, which the control unit of the device requires. The chain of the invention is a simplified extension of the functionality of the device. This goal is achieved by the fact that the device contains a control unit, a memory unit of the coefficients, a memory block of the language, a node for the multiplication of the network, | / ommutator. The outputs of the control unit are connected respectively to the first input of the switch, the input of the memory storage unit, through the coefficient storage unit with the second inputs of the group increment multiplication nodes and the first input of the multiplication unit. You move the adder through the memory block with the entrance to your input and through the multiplication node as- es - the second & 6 m switch, the outputs of which are connected to the inputs of the increment registers of the group. The device scheme contains the increment registers 1. Summers of increments 2 and units of multiplying increments 3, node multiplying law 4, adder 5, memory bar 6, memory block coefficient 7, switch 8, control unit 9 and outputs 10 of the device. The proposed device works in the following way. The initial system of linear algebraic equations: xx equations has the form,,, 2, ..., The algorithm for solving the system of equations (using unknown increments is written in the following form: f, ...- 1, -, 1 ..dx Axf.MxG. i 1, 2, ..., Kf ik 1, 2, ..., where M i are the scale factors (1), selected based on the requirements of the convergence of the algorithm and the specified time for the system of equations ( 1). In the initial state, the coefficients a, the system of equations (1) are written down by a memory block of coefficients 7, and the values of b; -o are kept in the memory block Ti nezok 6. Initial values of unknown unknowns) O is entered into increment adders 2., each k iteration; calculations, contains n cycles according to the number of rows of the solved system of equations (1). In the -th cycle, the coefficients (j ", c) are output from the memory block of the coefficient 1,. And the second 7 inputs to the second inputs of the multiplication units of the increments 3, the first inputs of which receive increments Ax from the increment registers 1. The results of the outputs of the outputs j – X multiplications of the increments 3 enter the group of inputs of the adder 5, to the other input of which the value (-and new At the output of the memory block of the previous iteration of the loop 6. At the output of the adder 5, a new value of the i -th trace is formed. which is stored in memory block 6 and fed to the second input of the mind node; sheath failure 4, the first input of the KOTOpoj is supplied with the value Mj from the output of the coefficient memory 7. The increment of the unknown at the output of the multiplication node 4 is Dx is fed through the switch 8 to the input of the i-th register of increments 1, where it is stored, and to the input of the -th increment combiner 2, in which the full value of the unknown unknown k is formed. In the next cycle, the (it i) -th line of the system of equations (1) is processed in accordance with algorithm (2) j, as a result of which a value unknown to X is calculated. After processing all rm lines, similar calculations are performed on (+ 1) iteration, etc., to achieve the specified accuracy of the solution. The sequence of switching / switching the switch 8 and outputting coefficients and nets of blocks 7 and 6 is carried out using the control unit 9, the control unit 9 also provides control signals for changing the scale M i (M; can be a multiple of two), which can be performed in the process of operation of the device as it approaches the desired solution. The technical and economic effect of the invention is that the proposed device has a significantly smaller amount of equipment than the known ones. In known devices, integrators are also used, which are equivalent in hardware costs to 4-5 increment registers, (n + n) multiplication units for increments and (- adders, while in the proposed device, ii increment registers are used, (and + 1) multiplication units increments and one adder. The memory blocks of the coefficients and the residual in the known devices are hardware combined with the integrators and multipliers