RU2190874C2 - Arithmetic device for calculating fast fourier transformation - Google Patents

Abstract

FIELD: computer science. SUBSTANCE: device has registers, multipliers and adders. EFFECT: high speed calculations; simplified design. 3 dwg

Description

 The invention relates to the field of computer technology and is intended to build devices for digital signal processing, in particular processors for fast Fourier transform and fast Hartley transform.

 It is known "Device for the multiplication of complex numbers" (a / s 1297034, G 06 F 7/49, 03.10.85,).

This device does not provide:
a) the necessary simplicity of hardware implementation;
b) the necessary speed due to the complexity of controlling the computing process.

 Closest to the claimed technical solution is the prototype "Arithmetic device for performing fast Hartley-Fourier transform" (assigned patent 2125290, 6 G 06 F 7/14, application 96105426/09 (009126) from 03.20.96), containing registers, switches, multipliers with drives.

 This device is designed to build digital signal processing devices, in particular processors for fast Fourier transform and fast Hartley transform.

This device does not provide:
a) the necessary simplicity of hardware implementation;
b) the necessary speed.

The invention consists of:
- to simplify the circuit of the device due to the use of multipliers and adders instead of switches and multipliers with drives;
- a significant increase in the speed of the device, achieved by pipelining the process of calculating the basic operation ("butterfly") of the FFT or BPH algorithm;
- to increase the speed of the device, achieved due to the regularity and ease of control of the computing process of the arithmetic device to perform FFT or BPH.

 For this, three registers, three multipliers, three adders are introduced into a device containing five registers.

 The invention will be apparent from the following description and the accompanying drawings.

In FIG. 1 shows a diagram of an arithmetic device for performing the BPH algorithm;
In FIG. 2 shows a timing diagram of the operation of an arithmetic device.

The following notation is used in the drawings and text:
1. The first data entry.

 2. Second data input.

 3. Input control multipliers.

 4. Third data entry.

 5. Fourth data entry.

 6. The first entry of the recording control.

 7. The first adder control input.

 8. Fifth data entry.

 9. Login control.

 10. Sixth data entry.

 11. The second entry control recording.

 12. The second adder control input.

 13. The third entry control recording.

 14. The fourth entry is a recording control.

 15. The first register.

 16. The second register.

 17. The third register.

 18. Fourth register.

 19. Fifth register.

 20. Sixth register.

 21. The first multiplier.

 22. The second multiplier.

 23. The first adder.

 24. The second adder.

 25. The third multiplier.

 26. The third adder.

 27. Seventh register.

 28. Eighth register.

 29. The first output of the result.

 30. The second output of the result.

 The arithmetic device for calculating the fast Hartley-Fourier transform, performing the basic Hartley-Fourier operation in the pipeline (see figure 1), includes eight registers, three multipliers, three adders.

 To the information inputs of the first register 15, second register 16, third register 17 and fourth register 18 are connected respectively the first data input 1, the second data input 2, the third data input 4 and the fourth data input 5. The control inputs of the register 15-18 are connected to the first the recording control input 6. To the information inputs of the fifth register 19 and sixth register 20 are connected, respectively, the fifth data input 8 and the sixth data input 10. Inputs of the write control registers 19, 20 are connected to the second input of the write control 11.

 The output of the first register 15 and the output of the second register 16 are connected respectively to the first and second information inputs of the first multiplier 21. The output of the third register 17 and the output of the fourth register 18 are connected respectively to the first and second information inputs of the second multiplier 22. The control inputs of the multipliers 21 and 22 are connected to the control input of the multipliers 3. The output of the first multiplier 21 and the output of the second multiplier 22 are connected respectively to the first and second information inputs of the first adder 23. The control input of the adder 23 is connected to the first control input of the adder 7. The output of the first adder 23 is connected to the first information input of the second adder 24. The output of the fifth register 19 is connected to the second information input of the second adder 24 and to the first information input of the third multiplier 25, the second information input of which is connected to the output sixth register 20. The control inputs of the adder 24 and the multiplier 25 are connected to the control input 9.

 The output of the second adder 24 is connected to the information input of the seventh register 27 and to the first information input of the third adder 26, the second information input of which is connected to the output of the third multiplier 25. The control input of the adder 26 is connected to the second control input of the adder 12. The output of the third adder 26 is connected to the information the input of the eighth register 28. The inputs of the write control registers 27, 28 are connected respectively with the third input of the write control 13 and the fourth input of the write control 14. The outputs of the seventh and direct registers 27, 28 are connected respectively to a first and a second result output 29, and 30 are informational device outputs.

 The device operates as follows.

где p, t - размерности матриц A, B, Q, F, G на разных итерациях.The FFT matrix recurrence algorithm described in a / c 633426, G 06 F 15/332, 03/13/89, is represented by the following formulas:

where p, t are the dimensions of the matrices A, B, Q, F, G at different iterations.

p = 2 ^m-1 ; t = 2 ^rm ; p * t = 2 ^r-1 ; r = log ₂ N, where m is the iteration number, m = 1, 2, 3, .. .., r, N = 2 ^r is the dimension of the processed data array;
the matrices A _p ^t , B _p ^t are the halves of the data array at the corresponding iteration;
matrices F _p ^t , G _p ^t are the halves of the results array at the corresponding iteration;
Q _p ¹ is the first column vector of the weight matrix Q _p ^t at the corresponding iteration.

The operation B _p ^t * Q _p ¹ is the static (elementwise) product of the matrix B _p ^t and the column vector Q _p ¹ .

Если взять N = 2, то формулы (1) принимают вид:

Формулы (2) представляют собой известное выражение базовой операции БПФ - "бабочки".Weights are represented by the following expression:
Q (k) = exp (-j2π (k-1) / N),
where k = 1, 2, 3, ..., N / 2;

If we take N = 2, then formulas (1) take the form:

Formulas (2) are a well-known expression of the basic FFT operation - “butterflies”.

где a, b, f, g, q - действительные части комплексных чисел A, B, F, G, Q, а α,β,γ,φ,σ - мнимые части этих чисел. Как показано в описании патента 2125290, 6 G 06 F 7/14, заявка 96105426/09 (009126) от 20.03.96 г. (название патента: "Арифметическое устройство для выполнения быстрого преобразования Хартли-Фурье"), формулы (2) можно представить в виде двух скалярных произведений матриц на вектор-столбцы:

Предлагаемое арифметическое устройство вычисляет операцию "бабочка" как матричную: вычислением скалярного произведения (3). Можно представить вычислительный процесс по формулам (3) с использованием математического знака суммирования:

где ψ_i и δ_i - числа a, b, -β, -a,1,q σ, 2, a θ_i и μ_i - числа α,β,b,-α, 1, q, σ и 2.The arithmetic device performs the "butterfly" FFT in accordance with formulas (2). We take into account that the numbers A, B, Q, F, and G are complex. Denote:

where a, b, f, g, q are the real parts of the complex numbers A, B, F, G, Q, and α, β, γ, φ, σ are the imaginary parts of these numbers. As shown in the description of patent 2125290, 6 G 06 F 7/14, application 96105426/09 (009126) of 03/20/96 (patent name: "Arithmetic device for performing fast Hartley-Fourier transform"), formulas (2) can represent in the form of two scalar products of matrices by column vectors:

The proposed arithmetic device calculates the butterfly operation as a matrix: by calculating the scalar product (3). One can imagine the computational process according to formulas (3) using the mathematical sign of summation:

where ψ _i and δ _i are the numbers a, b, -β, -a, 1, q σ, 2, a θ _i and μ _i are the numbers α, β, b, -α, 1, q, σ and 2.

представляют собой операции скалярного умножения.Amounts

represent scalar multiplication operations.

 The scalar product algorithm allows you to organize the process of computing the "butterfly" FFT in the pipeline, i.e. the result of the “butterfly” will be issued every measure (numbers f and φ, g and γ), which significantly increases the speed of computing the entire FFT algorithm.

Thus, it is possible to perform calculations in 4 clock cycles of multipliers and adders. We believe that the cycle of multiplication is equal in duration to the cycle of addition (subtraction). On the third measure, the results f and φ appear. On the fourth measure, the results g and γ appear.
The conveyor is filled in 4 steps, then the results of the calculation of the “butterflies” (numbers f and φ, g and γ) appear on the output every step.

где р=2^m-1, t=2^r-m, m=1, 2, 3, ..., r;
р, t - размерности матриц

на разных итерациях;
С_p ¹ и S_p ¹ - первые вектор-столбцы матриц весовых коэффициентов С_p ^t и S_p ^t на соответствующей итерации;
r - число итераций;
m - номер итерации;
N - длина исходного массива, N=2^r.Hartley matrix fast recurrence matrix algorithm (BPH) with time decimation described in RF patent 2071221, 6 G 06 F 17/14, application 94024301/09 (023698) dated 06/29/94 (title of the invention: "Processor for fast conversion Hartley ") is represented by the following formulas:

where p = 2 ^m-1 , t = 2 ^rm , m = 1, 2, 3, ..., r;
p, t are the dimensions of the matrices

at different iterations;
C _p ¹ and S _p ¹ are the first column vector vectors of the matrices of weight coefficients C _p ^t and S _p ^t at the corresponding iteration;
r is the number of iterations;
m is the iteration number;
N is the length of the original array, N = 2 ^r .

получена из матрицы В_p ^t. Строки матрицы

кроме первой, представлены строками матрицы В_p ^t, размещенными в обратном порядке (инверсия строк).The operation B _p ^t * C _p ¹ is the elementwise (static) multiplication of the columns of the matrix B _p ^t by the column vector C _p ¹ . Matrix

obtained from the matrix B _p ^t . Matrix Rows

except the first one, they are represented by the rows of the matrix B _p ^t placed in the reverse order (inversion of rows).

Weights are represented by the following expressions:
C (k) = cos (2π (k-1) / N); S (k) = sin (2π (k-1) / N); where k = 1, 2, 3, ..., N / 2.

Формулы (6) можно представить в виде скалярного произведения матрицы на вектор-столбец:

где

входные действительные числа; F, G - выходные действительные числа (результат счета); С и S - весовые коэффициенты.If we take N = 2, then the basic BPH operation ("butterfly") will be described by the expression:

Formulas (6) can be represented as the scalar product of a matrix by a column vector:

Where

input real numbers; F, G - output real numbers (counting result); C and S are weights.

где α_i,β_i - числа

Сумма

представляет собой операцию скалярного умножения.As shown in the description of patent 2125290, 6 G 06 F 7/14, application 96105426/09 of 03.20.96 (patent name: "Arithmetic device for performing fast Hartley-Fourier transform"), formulas (7) can be represented using mathematical sign of summation:

where α _i , β _i are numbers

Amount

is a scalar multiplication operation.

 The scalar product algorithm here, as in the case of the FFT, allows you to organize the process of computing the “butterfly” of the BPH in the pipeline, i.e. the result of the “butterfly” will be issued every measure (numbers F and G), which significantly increases the speed of computing the entire BPH algorithm.

 The calculation of the "butterfly" BPH is performed for 4 clock cycles of multipliers and adders. On the third bar, the result F appears, and on the fourth bar - the result G.

 The conveyor is filled in 4 steps, then the results of the calculation of each subsequent "butterfly" (numbers F and G) appear on the output every step.

для БПФ и БПХ. Поэтому в дальнейшем будет рассмотрен процесс вычисления "бабочки" БПХ.As we can see, the formulas for calculating the butterfly operation are similar

for FFT and BPH. Therefore, in the future, the process of calculating the “butterfly” of the BPH will be considered.

 In FIG. 1 is a diagram of an arithmetic device for performing a basic BPH operation in a conveyor.

Регистры 15-20 осуществляют прием и хранение этих чисел. Указанные числа записываются в регистры параллельным кодом. Регистр 15 принимает и хранит число В, регистр 16 - число С, регистр 17 - число

регистр 18 - число S, регистр 19 - число A, а регистр 20 - число 2. По входам 6 и 11 устройства на входы управления записью регистров поступают коды записи.At the inputs 1, 2, 4, 5, 8, 10, real numbers enter the arithmetic device

Registers 15-20 receive and store these numbers. The indicated numbers are written to the registers in parallel code. Register 15 receives and stores number B, register 16 - number C, register 17 - number

register 18 is the number S, register 19 is the number A, and register 20 is the number 2. At the inputs 6 and 11 of the device, write codes are received at the inputs of the register control.

 The arithmetic device processes incoming real numbers according to formulas (7). Only the operation of multiplying the number A by 1 is not performed, as excessive. As the conveyor ticks are fulfilled, real numbers come from the outputs of the registers 19 and 20 and are mixed into the scalar product in accordance with (7). At the inputs 3, 7, 9 and 12 of the device, the corresponding control codes are sent to the multipliers 21, 22, 25 and the adders 23, 24 and 26. The multipliers and adders perform the operation of computing the “butterfly” of the BPH by the clock, and each time the result is transmitted further to the next stage of the conveyor, and the previous stage is ready to process new operands. Three steps of the conveyor’s work are spent on calculating the result F and one step on calculating the result of G. Let us follow the steps of how the calculations are performed.

 1. From register 15, operand B goes to the first input of multiplier 21. From register 16, operand C goes to the second input of multiplier 21. Operands B and C are multiplied in multiplier 21 and the result is stored at the output of multiplier 21.

поступает на первый вход умножителя 22. Из регистра 18 операнд S поступает на второй вход умножителя 22. Операнды

и S перемножаются и результат запоминается на выходе умножителя 22.At the same time from the register 17 operand

arrives at the first input of the multiplier 22. From the register 18, the operand S goes to the second input of the multiplier 22. The operands

and S are multiplied and the result is stored at the output of the multiplier 22.

поступает на первый вход сумматора 23. С выхода умножителя 22 произведение

поступает на второй вход сумматора 23. Поступающие операнды суммируются в сумматоре 23 и результат запоминается на выходе сумматора 23.2. From the output of the multiplier 21 works

goes to the first input of the adder 23. From the output of the multiplier 22 product

arrives at the second input of the adder 23. The incoming operands are summed in the adder 23 and the result is stored at the output of the adder 23.

 3. From the output of the adder 23, the received amount goes to the first input of the adder 24. From the register 19, the operand A goes to the second input of the adder 24. The incoming operands are summed and the result is stored at the output of the adder 24. The first result is obtained — the number F. The number F is written to the register 27.

 At the same time, operand A from register 19 enters the first input of multiplier 25. From register 20, number 2 enters the second input of this multiplier. The operands are multiplied and the result is stored at the output of the multiplier 25.

 4. From the output of the adder 24, the number F (in the additional code) goes to the first input of the adder 26. From the output of the multiplier 25, the product Ax2 is fed to the second input of the adder 26. The incoming operands are summed in the adder 26 (in fact, the subtraction operation Ax2-F is performed). The second result is obtained - the number G. The number G is written to register 28. At the inputs 13 and 14 of the device, write codes are received at the recording control inputs of registers 27 and 28.

 Thus, the full cycle of computing the basic operation ("butterfly") of the BPH takes four clock cycles of the conveyor, in other words, four clock cycles of the multipliers and adders. The results of the calculation of the basic operation (numbers F and G) from the registers 27 and 28 are fed to the outputs 29 and 30 of the device with a shift by a clock between them.

 The conveyor is filled in 4 steps, then the results of the calculation of each next "butterfly" (numbers F and G) appear on the output of the device every step.

 The timing diagram of the arithmetic device when calculating several "butterflies" BPH is shown in figure 2.

2. The device according to claim 1, characterized in that r-1 arithmetic devices according to claim 1, 3r address shapers, 3r AND elements, r + 1 memory blocks, g read-only memory blocks, a control unit, a register are additionally introduced. Here r = log ₂ N is the number of iterations that must be performed to calculate the FFT or FFT of the data array of arbitrary dimension N = 2 ^r , r depends on the dimension of the data array N (r = 1, 2, 3, ...).

 Thus, the capabilities of the device according to claim 1 are expanded due to the implementation of a conveyor device for performing a fast Hartley-Fourier transform (i.e., an iteration pipeline calculating FFT or FFT) using the arithmetic device described in claim 1.

The invention according to claim 2 is:
- a significant increase in the speed of operation of the device, achieved by fully pipelining the process of computing the FFT or BPH algorithm by iterations (a pipeline by iterations is implemented) and using the arithmetic device described in paragraph 1 in the computing process;
- in ensuring the natural sequence of input and output information;
- to simplify the scheme, by introducing identical address formers made on ROM, in which sequences of addresses of numbers necessary for FFT or BPH for iterations are encoded;
- to increase the speed of the device, achieved due to the regularity and ease of control of the computing process of the FFT or BPH.

 The device will be clear from the following description and the attached drawing.

 In FIG. 3 shows a diagram of a conveyor device according to claim 2 for performing the BPH algorithm using a iterative conveyor.

The following notation is used in the drawing and text:
31. The arithmetic device according to claim 1.

 32. The information input of the conveyor device according to claim 2.

 33. Clock input.

 34. The first element of I.

 35. The second element of I.

 36. The third element of I.

 37. The first block of memory.

 38. Shaper addresses.

 39. The control unit.

 40. The output of the first memory block.

 41. The output of the first shaper addresses.

 42. The output of the second shaper addresses.

 43. The output of the third shaper addresses.

 44. The first block of read-only memory.

 45. The output of the first block of read-only memory.

 46. The output of the first arithmetic device according to claim 1.

 47. The second block of memory.

 48. The output of the second memory block.

 49. The first output of the control unit.

 50. The second output of the control unit.

 51. The third output of the control unit.

 52. The fourth output of the control unit.

 53. The fifth output of the control unit.

 54. The sixth output of the control unit.

 55. The seventh output of the control unit.

 56. The eighth output of the control unit.

 57. The ninth output of the control unit.

 58. The tenth output of the control unit.

 59. The eleventh output of the control unit.

 .......

 .......

 .......

 48 + 6r. 6th output of the control unit.

 49 + 6r. 6r + 1st output of the control unit.

 50 + 6r. 6r + 2nd output of the control unit.

 51 + 6r. 6r + 3rd output of the control unit.

 52 + 6r. The output of the rth arithmetic device according to claim 1.

 53 + 6r. r + 1st memory block.

 54 + 6r. Output r + 1-th block of memory.

 55 + 6r. Ninth register.

 56 + 6r. The information output of the conveyor device according to claim 2.

The composition of the conveyor device for performing fast Hartley-Fourier transform according to claim 2. (see figure 3) includes r arithmetic devices according to claim 1, r + 1 memory blocks, g permanent memory blocks, 3r address formers, 3r AND elements, control unit, register. Here r = log ₂ N is the number of iterations that must be performed to calculate the FFT or FFT of the data array of arbitrary dimension N = 2 ^r , r depends on the dimension of the data array N (r = 1, 2, 3, ...). The number of steps in the conveyor is r.

 The input of clock frequency 33 is connected to the first inputs of the first 34, second 35, third 36 elements AND, with which the first inputs of the elements And of the next r-1 stages of the conveyor device are connected, as well as the input of the control unit 39. First output 49, second output 50, the third output 51 of the control unit 39 is connected respectively to the second inputs of the first 34, second 35, third 36 elements And, the outputs of which are connected respectively the inputs of the first, second, third address makers 38. The information input of the conveyor device 32 is connected to the first input of the first memory unit 37, the second, third and fourth inputs of which are connected respectively with the fourth 52 fifth 53 outputs of the control unit 39 and with the output 41 of the first shaper 38. The output 40 of the first memory unit 37 is connected with the first input of the first arithmetic device 31, the second and the third inputs of which are connected respectively to the output 45 of the first block of read-only memory 44 and to the sixth output 54 of the control unit 39. The input of the first block of read-only memory 44 is connected to the output 43 of the third shaper 38. Output 42 is second Address generator 38 is coupled to a second input of the second memory unit 47, a first input coupled to an output 46 of the first arithmetic unit 31. The third and fourth inputs of the second memory block 47 are connected respectively to the seventh 55 and eighth 56 outputs 39 of the control unit.

 This concludes the description of the 1st stage of the conveyor device. The remaining r-1 steps are the same.

 The fifth input of the second memory unit 47 is connected to the output of the fourth address generator 38 (not shown in FIG. 3). The ninth 57th, tenth 58th and eleventh 59 outputs of the control unit 39 are connected to the second inputs of the fourth, fifth and sixth elements And, respectively (not shown in FIG. 3).

 ................

 ................

 ................

 The 6th output 48 + 6r of the control unit 39 is connected to the third input of the rth arithmetic device 31, the output 52 + 6r of which is connected to the first input of the r + 1th memory unit 53 + 6r. The 6r + 1st output 49 + 6r and 6r + 2nd output 50 + 6r of the control unit 39 are connected respectively to the third and fourth inputs of the r + 1st memory block 53 + 6r, the output 54 + 6r of which is connected to the information input of the ninth register 55 + 6r, the recording control input of which is connected to the 6r + 3rd output 51 + 6r of the control unit 39. The output 56 + 6r of the ninth register 55 + 6r is the information output of the conveyor device.

 The shaper of addresses 38 is made by a / s 1425667, G 06 F 9/36, 02.19.87.

 The device operates as follows.

The number of steps in the conveyor is r, i.e. equal to the number of iterations that must be performed to calculate the FFT or FFT of the data array of dimension N = 2 ^r . We will consider a conveyor device for calculating the FEC.

Iteration calculations are performed according to the BPH matrix recurrence algorithm (5). The initial information in the form of an array of real numbers of length N = 2 ^r enters in the natural sequence to the information input of the conveyor device 32 and is recorded in the first region of the first memory block 37. The information arrives with the clock speed of the conveyor of the arithmetic device according to claim 1. The recording signals are received from the output 52 of the control unit 39. The input clock frequency 33 receives clock pulses. After the entire array of length N = 2 ^r is recorded in the first region of the first memory block 37, the recorded information from the first region is overwritten without changing the order in the second region of the first memory block 37, and in the first region of the memory block 37 from the information input 32 the next input array of length N begins to be written. At this time, the first iteration of the BPH algorithm begins to be executed above the array located in the second region of the first memory block 37. Switching of the first and second regions of the first memory block 37 is carried out by a signal from the output 53 of the control unit 39. As memory blocks 37, 47, ..., 53 + 6r microchips of a dual-port memory can be used, which allow writing and reading information simultaneously.

и адреса для записи результатов "бабочки" - чисел F и G в соответствии с временной диаграммой работы арифметического устройства по п.1 (фиг.2).Consider the work of the 1st stage of the conveyor device, i.e. execution of the first iteration of the BPH algorithm. From the outputs 49, 50 and 51 of the control unit 39, the corresponding permission signals are supplied to the elements I34, I35 and I36. Clock pulses from the outputs of the elements I34, I35 and I36 are respectively supplied to the inputs of the first, second and third address generators 38. All three address generators 38 begin to generate operand addresses

and addresses for recording the results of the “butterfly” - the numbers F and G in accordance with the time diagram of the arithmetic device according to claim 1 (figure 2).

поступающие во вторую область первого блока памяти 37. С выхода 40 блока памяти 37 операнды

соответствующие этим адресам, параллельным кодом поступают на первый вход первого арифметического устройства 31.At the output 41 of the first shaper of addresses 38, starting with the 1st “butterfly” of the BPH, operand addresses appear

coming into the second region of the first memory block 37. From the output of 40 memory block 37 operands

corresponding to these addresses, a parallel code is supplied to the first input of the first arithmetic device 31.

 At the output 43 of the third address generator 38, the addresses of the operands C, S and the number 2 appear at the input of the first block of read-only memory 44. From the output 45 of the first block of read-only memory 44, the operands C, S and the number 2 corresponding to these addresses are sent to the parallel code by the second input of the first arithmetic device 31.

 The arithmetic device 31 processes the incoming real numbers according to formulas (7) - as described above. The conveyor is filled in 4 cycles, then the results of the calculation of each next “butterfly” of the BPH (numbers F and G) appear at the output of the arithmetic device 31 every cycle (in accordance with the time diagram of the operation shown in FIG. 2).

 The second address generator 38 generates addresses for recording the numbers F and G; then these addresses from the output 42 of the second address former enter the first area of the second memory unit 47. The results of the calculation of the “butterflies” - the numbers F and G appearing at the output of the first arithmetic device 31, are recorded at these addresses in the first area of the memory unit 47. The recording signals come from the output 55 of the control unit 39.

 The operation of address formers 38 is described in more detail in RF patent 2071221, 6 G 06 F 17/14, application 94024301/09 of 06/29/94, title of invention: "Processor for fast Hartley conversion".

 The control signals of the multipliers and adders 21, 22, 23, 24, 25, 26, as well as the control signals for writing to the registers 15, 16, 17, 18, 19, 20, 27 and 28 of the arithmetic device 31 are received from the output 54 of the control unit 39.

Thus, all N / 2 “butterflies” of the first iteration of the BPH algorithm are calculated at the first stage of the conveyor device. In time, the execution of the first iteration (like all others) takes N / 2 clock cycles of the conveyor of the arithmetic device 31 (the clock cycle of the conveyor is indicated by T _ap in figure 2).

 After the end of the first iteration count, the results array accumulated in the first region of the second memory block 47 is overwritten without changing the order in the second region of the memory block 47, and the results of the calculation of the 1st iteration of a new input array of length N begin to be written again into the first region of the memory block 47 , which was previously in the first region of the first memory block 37 and was overwritten in the second region of the memory block 37. At the same time, in the first region of the memory block 37 from the information input of the conveyor devices and 32, the next input array of length N begins to be recorded with the cycle time of the conveyor of the arithmetic device 31.

 Switching of the first and second regions of the second memory unit 47 is carried out by the signal from the output 56 of the control unit 39.

 Similar to the work of the 1st stage, the second stage of the conveyor device performs the second iteration of the BPH algorithm. Then, at the end of the 2nd iteration count and overwriting information from the first areas of the memory blocks to the second areas, the third step performs the third iteration, etc.

 At each moment of time, each stage of the conveyor device performs its own iteration of the BPH algorithm: 1st stage - the first iteration, 2nd stage - the second iteration, etc. The input information is supplied to the information input 32 with a clock cycle of the conveyor of the arithmetic device 31.

 Each time after completion of the iteration, rewriting information from the first areas of memory blocks 37, 47, etc. in the second areas of these memory blocks occurs synchronously for all memory blocks. The number of memory blocks is equal to the number of steps in the conveyor device plus one, i.e. equal to r + 1.

 All r stages of the conveyor device have the same scheme as the 1st stage and perform corresponding iterations in the same way as described for the 1st stage. The number of outputs of the control unit 39 is proportional to the number of steps of the conveyor device.

и адреса для записи результатов "бабочки" формируются соответствующими формирователями адресов 38 r-й ступени (на фиг.3 не показаны).Consider the work of the last, rth stage of the conveyor device (with the length of the input data array N = 2 ^r ). This step performs the last, rth iteration of the BPH algorithm. Iteration is performed similarly to the previous ones. The results of calculating the “butterflies” - the numbers F and G from the output of the rth arithmetic device 31 are recorded in the first region r + 1 of the first memory block 53 + 6r. The recording signals come from the output 49 + 6r of the control unit 39. The addresses of the operands

and the addresses for recording the results of the “butterfly” are formed by the corresponding address generators 38 of the rth step (not shown in FIG. 3).

At the end of the calculation of the last, N / 2nd “butterfly”, the last, rth iteration, in the first region of the r + 1st memory block 53 + 6r, the desired array of the Hartley spectrum (array of discrete Hartley – DPC transformation) will be accumulated in the natural order following. Then, according to the signal from the output 50 + 6r of the control unit 39, the Hartley spectrum array is overwritten without changing the order from the first region to the second region r + 1 of the 53 + 6r memory block. After this stage of the conveyor device, the corresponding iterations begin to be performed, and the resulting Hartley spectrum from the output of 54 + 6r r + 1-th memory block sequentially, with the clock cycle T _{ap of the} conveyor of the arithmetic device 31, begins to be recorded in the register 55 + 6r. The write code is input to the write control input of the register 55 + 6r from the output 51 + 6r of the control unit 39. Then, the obtained Hartley spectrum (DPC) is fed to the information output of the conveyor device 56 + 6r.

The conveyor device according to claim 2 is filled in for r • N / 2 clock cycles of the conveyor of the arithmetic device 31, then the desired Hartley spectrum of the source arrays appears in the natural sequence on the information output 56 + 6r with the clock cycle T _{ap of the} conveyor of the arithmetic device 31 according to claim 1 Moreover, first the 1st array of DPH with the length N = 2 ^r will be released, followed by the 2nd array, then the 3rd, etc. Those. the resulting DPC sequence will be output by arrays (parts) of length N = 2 ^r , which correspond to the original data arrays also of length N = 2 ^r supplied to information input 32.

 Thus, a complete pipelining of the calculation process of the BPH algorithm is achieved.

Claims (1)

 An arithmetic device for calculating the fast Hartley-Fourier transform, containing the first to fifth registers, characterized in that the sixth, seventh and eighth registers, the first, second and third multipliers, the first, second and third adders are introduced, the first and sixth inputs the data of the arithmetic device are connected respectively to the information inputs of the first to sixth registers, the recording control inputs of the first to fourth registers are connected to the first input of the recording control of the arithmetic device, control inputs by writing the fifth and sixth registers - with the second input of the recording control of the arithmetic device, the outputs of the first and second registers - with the first and second information inputs of the first multiplier, respectively, and the outputs of the third and fourth registers - with the first and second information inputs of the second multiplier, control inputs of the first and the second multipliers - with the control input of the multipliers of the arithmetic device, the outputs of the first and second multipliers - respectively, with the first and second information input the first adder, the control input of which is connected to the first control input of the adder of the arithmetic device, and the output is connected to the first information input of the second adder, the second information input of the second adder is connected to the output of the fifth register and to the first information input of the third multiplier, the second information input of which is connected to the output of the sixth register, the control inputs of the second adder and the third multiplier with the control input of the arithmetic device, the output of the second adder with information the input of the seventh register and with the first information input of the third adder, the second information input of which is connected to the output of the third multiplier, the control input of the third adder is with the second input of the adder control of the arithmetic device, the output of the third adder is with the information input of the eighth register, the seventh and the eighth registers - respectively, with the third and fourth inputs of the recording control of the arithmetic device, and the outputs of the seventh and eighth registers - respectively first and second outputs of the arithmetic unit result.

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