SU1061150A1 - Device for executing haar orhtogonal transoform of digital signals - Google Patents

Abstract

DEVICE FOR ORTHOGONAL TRANSFORMATION OF DIGITAL SIGNALS BY HAAR, containing an arithmetic unit, three groups of delay blocks, two groups of shift blocks consisting of serially connected shift registers, and a block: synchronization, the first output of which is connected to the clock inputs of the shift registers in each shift block, characterized in that, in order to simplify the device, it contains five re-, key switches, first, second and third group of delay blocks consisting respectively of and {2 is the input sample size), P- 1 and one delay unit, pervag. and the second group of blocks of shift consist of n - 1. blocks of shift, and i.e. (i 1, ..., and - 1) blocks of shift of the first and second groups each, respectively, of and, + n - i serially connected registers shift, the first information input of the first switch is the information input of the device, the information inputs of the first switch from the first to the AND, and through the socket, the delay blocks of the first group are connected to the same information inputs of the second switch, the outputs of the first and second switches are connected to the inputs of the arithmetic unit, the outputs of the sum and difference of which are connected to the information inputs of the third and fourth switches, respectively, and the output of the third switch through the corresponding delay block of the second group of prdklyuchny, to (+ 1) -th information first switch, p -ft output of the third the switch is connected to the first information input of the fifth switch, j is the output (J 1, ..., n) of the fourth switch connected to the input of the first shift register in the j-th shift block of the first group, the outputs are register in the shift in the 1st shift block of the first group are connected to the inputs of the shift register of the same name in the Jth block of the shift of the second group, the output (+ n - i) -ro of the shift register in the i-th shift block of the second group, except ( p-1) of the second group shift unit, connected to the input of the first shift register in the (+ 1) -th shift unit of the second group, -OUT the third shift register in the (n-lJ-M shift unit of the second group is connected to the information input of the unit the delay of the third group, the output of which is connected to the second information input of the first switch, the output of the fifth The switch is the output of the device, the second output of the synchronization unit is connected to the synchronization inputs of the first, second, third and fourth switches, the third output of the synchronization unit is connected to the synchronization input of the fifth switch, the outputs of the synchronization block from the fourth to (and + W) are connected to control inputs to the shift registers of the respective shift blocks of the second group.

Description

The invention relates to automation and computer technology and can be used in digital communication systems for building digital filtering devices, image compression and contour extraction based on the fast Haar transform (VPH) algorithm. A device that calculates the Haar transform coefficients is known. The disadvantages of the known device are complexity and cumbersome. The closest to the invention is a device for orthogonal conversion of digital signals according to Haar, containing two serially connected unit modules on the base each of which contains two a shift register that implements the delay functions, and an arithmetic unit To order the calculated coefficients and convert them to a sequential flow The device contains a group of registers, each of which is connected to one of the modules. The operation of the entire device is synchronized by the control unit, consisting of a counter and a matrix of permanent memory of its ROM 2 device. According to the structure, the said device relates to a flow multiprocessor circuit for performing a fast orthogonal transform. This structure is suitable for building high-speed systems. For n 2 clock cycles of the input signal, the device, with a characteristic delay for all flow diagrams, yields n transform coefficients. However, in this device, each subsequent arithmetic unit during the conversion time is half as many subtraction addition operations than the previous one. Thus, the first arithmetic unit calculates half of all transform coefficients, with the first arithmetic unit operating only half of the total conversion time. Each subsequent arithmetic block is occupied by calculations two times less time than the previous one, i.e. the first arithmetic unit at the same time performs the same calculations as all the others together. In addition, the device contains many arithmetic units, which are also used outside the floor. Noah A disadvantage of the known device is its complexity. The purpose of the invention is to simplify the device. The goal is achieved by the device for orthogonal conversion of digital signals according to Haar, containing an arithmetic unit, three groups of delay blocks, two groups of shift blocks consisting of serially connected shift registers, and a synchronization block, the first output of which is connected to the clock inputs of shift registers in each shift block, contains five switches, the first, second and third groups of delay blocks. consist of n respectively (2 is the input sample size), P is 1, and one delay block and, the first and second groups of shift blocks consist of h - 1 shift blocks each, with the 1st (1, ..., c -1) blocks of the shift of the first and second groups consisting respectively of 211-1 + n - 1 serially connected shift registers, the first information input of the first switch is the information input of the device, the information inputs of the first switch from the first and-and through the corresponding delay blocks of the first group are connected to the same information inputs of the second switch, the outputs of the first and second switches are The outputs are the sum and difference outputs that are connected to the information inputs of the third and fourth switches, respectively, and the output of the third switch through the corresponding delay block of the second group is connected to the (i + 1) -th information input of the first switch, and - and the output of the third switch is connected to the first input-, formational input of the fifth switch, j - and output (j 1, ..., and), the fourth switch is connected to the input of the first shift register in the) -th shift unit of the first group, reg Shifters in the i-th shift block of the first group are connected to the inputs of the shift register of the same name in the 1st block of the second group, the output (+ ni) -ro of the register in the shift unit of the second group, except vi - 1) -th shift block of the second group connected to the input of the first shift register in the (l + 1) -th shift unit of the second group, the output of the third shift register in the (n -1) -th shift unit of the second group is connected to the information entry of the third group, the output of which is connected to the second the information input of the nth switch, the output of the nth switch the output of the device, the second output of the synchronization unit is connected to the synchronization inputs of the first, second, third and fourth switches, the third output of the synchronization unit is connected to the synchronization input of the fifth switch, the outputs of the synchronization unit from the fourth through (3) are connected to the control inputs entering into shift registers of the corresponding shift blocks of the second group.

. FIG. 1 shows a functional diagram of an apparatus for orthogonal digital conversion of signals according to Haar (N 16); FIG. 2 is a graph. Sequence of computational BPH calculations for n 16; FIG. Temporary switch operation diagrams.

The device contains information input 1, arithmetic unit 2, switches E - 3 and 4, blocks 5c - Sg shift, consisting of serially connected shift registers, blocks 6 / - 6g delay, device output 7, block 8 synchronization, bus 9 t - 11 and 12 | - l2a sync.

Each delay unit in the device contains one shift register, storing the incoming number until the next one arrives. To delay multi-digit numbers, several shift registers must be connected in parallel.

FIG. 2, the number of the cycle during which it is performed is indicated next to each basic point-to-point conversion operation.

FIG. 3 numbers 1-16 denote the samples of the first input sample, and 1. - the first seven counts of the subsequent input sample. The first second, third and fourth positions of the switches 5-5 are shown in FIG. 3 vertical number 1 - 4.

The device works as follows.

With the frequency of clock pulses to the device input samples of a discrete signal. For the even cycles of 2, 4, 6, 8, 10, 12, 14, and 16, the arithmetic unit performs the eight basic operations of the two-point transformations of the first and second, third and fourth, fifth and sixth, seventh and eighth, ninth and tenth , eleventh and twelfth, thirteenth and fourteenth, fifteenth and sixteenth counts respectively, i.e. the first stage of the transformation on the column BPH (Fig. 2). The calculated differences of these pairs of samples are the Haar coefficients from the ninth to the sixteenth, respectively, and are fed to the input of block 5 | shear.

On odd clock cycles, the arithmetic unit performs the seven remaining basic operations, corresponding to the second, third, and fourth stages of the conversion on the BPH graph (Fig. 2}.

Switches 3j - 2n work the same way.

 So, on the second clock, the switches 3–3 are switched on to the first position (Fig. 3), then the second countdown

A2 from the device input through switch 3, and the first countdown 01

10 from the output of the delay block 6 through the switch 32 enters the inputs of the arithmetic unit 2. The outputs of the arithmetic unit receive the calculated sum (0) and the difference

5 (01, - Qj). The sum through the switch 3 is fed to the input of the delay unit 6, and the difference, which is the ninth Haar coefficient, through the switch 3 is fed to the input

0 block 5 shift.

In the third cycle, the switches 3 / (- 3j are turned on to the third position. The third count O} goes to the input of the device and to the input of block 6

5 and is remembered in the latter.

In this cycle, the arithmetic unit performs the basic operation on

the previous sample count. I

On the fourth cycle switches

0 3i - 3 included in the first position. This means that the fourth count Ots is received from the input of the device through switch 3 at the inputs of the arithmetic unit. and the third countdown

5 - from the output of the block 6. delays through the switch Calculated difference (Oz i with the tenth Haar coefficient, through switch 3 will arrive at the input of the block

0 shift, and the sum (0 + 3 through the switch Zz will go to the input of the delay unit 6y, while the earlier sum recorded in it (O, + Q) will go to block b, delay.

On the first tact switches

5 3 - 34 are included in the second position (Fig. 3). The device receives the fifth count Oj at the input; it is memorized in block 6 instead of the third count a. Amount (a + 014) through

switch 3 from the output of block 6, is fed to one input of the arithmetic unit, and the sum (ai + Og) through switch 3j from the output of block 6 goes to another input of the arithmetic block. The arithmetic unit 2 on the fifth cycle calculates the sum of (a, + O) + (04) and the difference (q + + π) - (a). The calculated difference is the fifth coefficient.

0 Haar and through switch 3 is fed to the input of block 5 cLvig, and the sum through the switch of block 6 input (3 delays, etc.

At the inputs 12, - 12 blocks Sj, 5

5 and 5 by filling in blocks 5; | , S-j

And memory, Ie on the first, fourth and sixth cycles of the subsequent sample. respectively, gating pulses from the synchronization block permitting the arrival of the Haar coefficients from block 5, 5, and 5y to blocks 5, 54, and 5. At the inputs 11, the clock frequency comes from the synchronization block 8, from which the conversion coefficients entered into blocks 5h, 5 and 5b / successively through the delay unit 6g are fed to the input of the switch 4.

At the input to the command 10 from the synchronization unit 8, the switch 4 is on every seventh clock cycle

included in the first position. Through it, output 7 of the device receives the first Haar coefficient. The next fifteen cycles, i.e. before the seventh cycle of the next sample, switch 4 is turned on to the second position and through it to the output 7 of the device, the remaining fifteen Haar coefficients arrive at the output of the block b% delay, etc.

The proposed device is much simpler known, because instead of and. Arithmetic blocks contains only one arithmetic block.

ah (2

X - basic operation i QrC

  2 3 L 5 6 7 8 .J 10 iii2 i.l ia 1516 l 9 lli. fi y

inTfrrfrrrrrrnfrrrrrri

Fig.Z

Claims (1)

A device for orthogonal conversion of digital signals according to Haar, comprising an arithmetic block, three groups of delay blocks, two groups of shift blocks consisting of series-connected shift registers, and a synchronization block, the first output of which is connected to the synchronization inputs of shift registers in each shift block, different the fact that, in order to simplify the device, it contains five switches, the first, second and third groups of delay blocks consist respectively of η (2 ^P is the volume of the input sample), η - 1 and one nth delay block, the first and second groups of shift blocks consist of η - 1. shift blocks each, and ί = β (<= 1, ..., and - 1) shift blocks of the first and second groups consist respectively of 2 ^{П 4} and, 2 ^ '' + η - ί of the shift registers connected in series, the first information input of the first switch is the information input of the device, the information inputs of the first switch from the first to the ηth through the corresponding delay units of the first group are connected to the same information inputs of the second switch, outputs first and second the switches are connected to the inputs of the arithmetic unit,) the outputs of the sum and difference of which are connected to the information inputs of the third and fourth switches, respectively, the 4th output of the third switch, through the corresponding delay unit of the second group, is connected to the ((+ 1) -th information input of the first switch , the pth output of the third switch is connected to the first information input of the fifth switch, the jth output (; = 1, ..., p) of the fourth switch is connected to the input of the first shift register in the jth shift block of the first group, the outputs of the shift registers in the 4th shift block of the first group are connected to the inputs of the same shift registers in the i-th shift block of the second groups, the output of the (2 ^П * '+ п-i) -ro shift register in the (th block ^{4 of the} shift of the second group, except for the (n -1) th shift block of the second group, is connected to the input of the first shift register in ( 4+ 1) th shift block of the second group, the output of the third shift register in the (n-1) th shift block of the second group is connected to the information input of the block the third group, the output of which is connected to the second information input of the fifth switch, the fifth switch output is the output of the device, the second output of the synchronization unit is connected to the synchronizing inputs of the first, second, third and fourth switches, the third output of the synchronization unit is connected to the synchronizing input of the fifth switch, outputs synchronization blocks from the fourth to (and + 3) -th ° are connected to the control inputs of entering into the shift registers of the corresponding shift blocks of the second group.