SU1566368A1 - Digital correlator - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase speed. In the correlator, for carrying out the threshold processing of the current random binary sequences, the maximum value of the mutual correlation function (ICF) of the base and current sequences is not determined, but the degree of difference between them is specified, while fixing those positions where the CCF exceeds the value of the specified threshold value, which is performed simultaneously in the CCF determination cycle. The correlator contains a block of 3 delays, elements AND 4, 7, 9, 14, 15, 21 triggers 8, 18, 30, blocks 10 threshold processing, frequency divider 11, counters 12, 28, 29 element OR 13, block 16 synchronization register 17, switches 19, 27. 1 Cp f-crystals, 2 ill.

Description

The invention relates to automation and computing and can be used in correlation extremal systems.

The aim of the invention is to increase speed.

FIG. 1 shows the structural scheme of the correlator; in fig. 2 - block diagram block diagram.

The correlator contains (Fig. .1) the first 1 and second 2 clock inputs, delay block 3, multiplication blocks C, information input 5, threshold input 6, And 7 elements, trigger 8, And 9 9 element threshold processing blocks 10 , frequency divider 11, counters 12, element OR 13, elements AND 14 and 15, included in block 10 of threshold processing, synchronization block 16, register 17 triggers 18, switch 19, information input 20, element 27, key 22, first 23, the second 24, the third 25 and the fourth 26 outputs of the synchronization unit 16, the switch 27, the counters 28 and 29, the trigger 30 and the output 31.

The synchronization unit 16 (Fig. 2) contains a generator of 32 clock pulses, an AND 33 element, a counter 34, a trigger 35, a one-shot 36, a delay element 37, an OR element 38, a 39 and AO one-shot, a trigger 41, element; -1RI 42 .

Block 16 works as follows.

When the supply voltage is applied to the device, the one-shot 39 produces a pulse, which sets the counter 34, the triggers 35 and 41, to the zero state and arrives at the output 23 of the unit. When the image signal generator (VIF) arrives at the first clock input of the first horizontal scanning pulse corresponding to the beginning of the base image line and, therefore, to the beginning of the basic random binary sequence received at the input 20 i of the correlator, the trigger 41 is set to

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the unit state and pulses from the generator of 32 clock pulses through the open element I 33 begin to arrive at the output 25 of the block and at the counter 34. The capacity of the counter 34 is N (where N is the length of the random sequences being processed). After N clock cycles, the signal from the output of the counter 34 sets the trigger 35 to one. The output signal of the trigger 35 is delivered to the one-shot 36, which produces a pulse arriving at the output 26 of the block, through the delay element 37 at the output 24 of the block and through the OR 42 element to the trigger 41. The trigger 41 is set to the zero state by closing AND 33. The arrival of clock pulses at block output 25 is stopped.

When the second horizontal pulse arrives from the VFR corresponding to the first current line of the image and, consequently, the first current random binary sequence received at the input 5 of the correlator, the trigger 41 is set to one state and the pulses from the generator 32 through the open element 33 begin to arrive on the output 25 of the block and on the counter 34. Next, the block 16 operates in the same way. At. When the SR is acquired from the next horizontal scanning pulse corresponding to the next current line of the image, the correlator unit 16 operates in the same way.

At the end of the frameframe sweep period with the VLF, a signal is fed to the second clock input — to the one-shot 40, which produces a pulse, which sets the correlator to the initial state.

The correlator works as follows.

Before the start of the measurement cycle, output 16 of block 16 receives the Initial Setup command, according to which the correlator receives the initial state.

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Trigger 8 accepts a zero state sequence.

from the front of my clock counter is 12 dodge. In the case of a mismatch of the horny signal signal, the juice 12 is reduced; the counters 12 are considered to coincide; if the threshold exceeds the moment when the content becomes zero, at its output the held J5 leads to gera 18.

wherein the input of the delay unit 3 through the switch 19 is connected to the input 20 of the correlator. Register 17, counters 12, counters 28 and 29, and frequency divider 11 are set to zero, with the result that key 22 is open.

Then, clock pulses are output from output 25 of block 16. A basic random binary sequence is recorded, which arrives synchronously with the clock pulses from input 20 in block 3 delays. After N clock cycles, the output trigger of frequency divider 11 switches to one state, closing key 22. Simultaneously switching trigger 8. Changing the state of trigger 8 causes switch 19 to take such a position that the delay unit 3 is closed in a ring. Simultaneously with the recording of the base binary sequence, the value of the threshold value is recorded into the counter 28 via the switch 27 with a parallel code.

On a Reset command from the output 2k of the block 16, the frequency divider 11 and the counters 12 are zeroed out, and the trigger 30 and the triggers 18 are set to one, with the key 22 being opened, and the switch 19 remaining in the same state. After the Reset command, clock pulses are sent to the device from output 25 of block 16, shifting the information in block 3 delays and gating elements AND 7. Synchronously with clock pulses from input 5 to the second inputs of multiplication unit k, the first random binary sequence is received, where it multiplies with the basic sequence.

The results of multiplication through the elements And 7 arrive at the first inputs of the threshold processing units 10. The second inputs of the threshold processing units 10 through the And 21 element arrive synchronously with the clock pulses of a series of pulses, the number of which determines the degree to which the base sequence differs from the current sequence. Since the outputs of the elements AND 14 and 15 of the block 10 of the threshold processing are connected respectively to the summing and subtracting inputs of the counter 12, then when the signals coincide

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with the arrival of the trailing edge of the clock pulse, the contents of the counter 12 are increased by one. If the sequence signals do not match and there is no threshold signal, the contents of counter 12 are reduced by one, i.e. counters 12 count the number of coincidence pulses exceeding the threshold value in the corresponding channels. At the moment when the contents of the counter 12 become zero, a single signal at its output of the sign of the zero contained J5 held leads to resetting of the trI1-ger 18.

Synchronously with the clock pulses arriving at the subtracting input of counter 28, the summing input of counter 29 is supplied with a sequence of threshold value signals, which leads to overwriting information from counter 28 into counter 29. The capacity of counters 28 and 29 is equal to the maximum value of the pulse sequence of setting the threshold value.

When the counter 28 is zeroed out, a single signal of the zero content sign from its output transfers the ger 30 to the zero state, which stops the arrival of clock pulses at the second inputs of the threshold processing units 10 and the summing input of the counter 29.

Through N ticks, the 1st trigger positions are fixed in which the mutual correlation function of the input sequences exceeds the specified threshold. At this moment, the output trigger of the frequency divider 11 switches to one state by closing the key 22, which stops the flow of clock pulses to the delay unit 3. At output 26 of block 16, a signal appears allowing the recording of information from triggers 18 to output register 17, as well as the threshold value from counter 29 through switch 27 to counter 28.

Therefore, before the arrival of the next Reset command, coming from the output 24 of block 16, the device is ready to process the next current binary sequence.

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Claims (1)

1. Digital correlator containing delay unit, first and second triggers, OR element, register, frequency divider, key, switch, AND element, counter, synchronization unit, N channels, each of which contains a multiplication unit, counter, first and second elements AND, the first output of the synchronization unit is connected to the register recording enable input, the zero input of which is connected to the first input of the OR element, the installation input of the first trigger O, and the second output of the synchronization unit the third output of which is connected to the second input of OR, the output of which is connected to the inputs of the O frequency divider and the counters of each channel, the information input of the frequency divider is connected to the information input of the key and the fourth output of the synchronization unit, the control input of the key is connected to the installation input of 1 of the first trigger and the output of the frequency divider, the key output is connected to the clock input of the delay unit, the information input of which is connected to the output of the switch, the first information and control inputs of which are connected respectively to the output of the delay unit and the output of the first trigger, the second information input of the substitute is the first input of the correlator, the first and second clock inputs of the synchronization unit are the same inputs of the correlator, the forward inputs of the first elements of the AND are connected to the second information input of the correlator, the inverse inputs of the elements AND of all channels are connected to the corresponding outputs of the delay unit s; the register output is the output of the correlator, characterized in that, for the purpose of higher. k 6bC iJ v4c G8II in Hfcro ADDITION,;, L is the second hour , second, t young man ate / .b, the second element And, in  the channel additionally introduced the third and fourth elements And and trig- 4 rep, and in each channel the output of the first element And is connected to the first input of the second element And, the output of which is connected to the inverse input of the third element And and the direct input of the fourth element And, the output the third element And is connected to the summing input of the counter, the subtracting input of which is connected to the output of the fourth element And, the output of the sign of zeroing the counter is connected to the input of the installation in the 0m trigger, the outputs of the trigger all the channels are connected to the corresponding inputs of the register, the third output of the synchronization unit is connected to the installation inputs of the second flip-flop and the triggers of all channels, the second output of the synchronization unit is connected to the zeroing inputs of the first and second counters, the fourth output of the synchronization unit is connected to the first input of the first And element, the second input which is connected to the output of the first trigger, and the output with the subtractive input of the first counter, the second inputs of the second And elements of each channel and the first input of the second And element, the second input which is connected to the output of the second trigger, and the output to the summing input of the second counter and the forward input of the third element AND and the inverse input of the fourth element AND of each channel, the first output of the synchronization unit is connected to the control input of the second switch, the first information input of which is setting the correlator threshold, the second information input of the second switch is connected to the output of the second counter, and the output is connected to the input setting the initial state of the first counter, the output of the zero feature is second input coupled to the installation of G second flip-flop. 2, a correlator according to claim 1, characterized in that the synchronization unit comprises three single vibrators, two triggers, a counter, a clock generator, a delay element, two OR elements and an AND element, the output of the first single vibrator being connected to the input of the delay element and the first input of the first OR element and the first first output of the block, the output of the delay element is the third input of the block, the input of the first duplicator is connected to the output of the first trigger, the installation input of which is connected to the installation input of the counter O second exit w the OR element and the output of the second OR element is the second output of the block; the input of setting 1 of the first flip-flop is connected to the output of the counter, whose information input is connected to the output of the AND element and is the fourth output of the block; responsibly with the output of the clock generator and the output of the second the trigger, the installation input of which is connected to the output of the first element OR, the first and second inputs of one-single vibrators, the input of the second single vibrator and the installation input to 1 of the second trigger are the corresponding OR elements connected respectively to the first and second clock inputs of the unit. with the second and third outputs single vibrators, the input of the second single vibrator, and the installation input to 1 of the second trigger are respectively the first dami block. 25 26 14 23