SU788409A1 - Phasing device - Google Patents

Description

(54) PHASE DEVICE

The invention relates to discrete information transfer devices and can be used, for example, in synchronization devices of data receiving and transmitting systems.

A phasing device is known, comprising a series-connected master oscillator, an And element, a frequency divider, an inhibiting unit and a trigger, the output of which is connected to another input of the And 1 element.

However, the known phasing device has a low phasing rate.

The purpose of the invention is to increase the speed of phasing.

For this purpose, a phasing device containing a series-connected master oscillator, an And element, a frequency divider, a prohibition unit and a trigger, the output of which is connected to another input of the And element, a code-recording gate is inserted between the output of the master oscillator and the second trigger input sequentially connected an additional element And the second frequency divider, the other input of which is connected to the output of the code recording valve, the first and second inputs of which are connected

respectively, to another output of the frequency divider and the output of the prohibition block, and the second output of the trigger is connected to another input of the additional element I.

The drawing shows a structural 5 electrical circuit of the proposed device.

The phasing device contains the master oscillator 1, the AND 2 element, the divider 3 frequencies, the prohibition block 4, the trigger 5, the additional AND 6 element, the second frequency divider 7 and the code recording gate 8. 8. The bus 9 is the output of the device.

The device works as follows.

The impulse of the initial setup, the trigger, 5 5 is set to one state, and all bits of dividers 3 and 7 frequencies - to the zero state. Through the open element And 2 pulses master oscillator 1 is fed to the input of the divider 3 frequency. The output pulses of the divider 3 frequency arrive 20 at the prohibiting input of the prohibition unit 4 and at the output of the device. An additional element And 6 while closed low potential from the second output of the trigger 5 and

the input of the second divider 7 frequency pulses do not pass.

The operation of the device when there are phase pulses at the input depends on the phase of arrival of the latter, i. if the phasing pulses are input to the prohibition unit 4 in phase with the output pulses of the splitter 3 frequency, then the output of the prohibition block 4 does not contain signals and the device works in the same way as described above.

If the phase of the input phasing pulse is different from the phase of the output pulse of the divider 3 frequency, the phase pulse passes through the prohibition block 4 and switches the trigger 5 to the zero state, blocking the element 2 and opening the additional element AND 6. At the same time, the pulse from the output of the prohibition block through gate 8, the code records in the bits of the second frequency divider 7 set the code inverse to the code containing the frequency divider 3 frequencies at a given time. The trigger 5 is switched by the falling edge of the pulse coming from the output of the prohibition block 4. The change in the states of the bits of the dividers 3 and 7 of the frequency under the influence of the pulses of the master oscillator 1 also occurs on the rear edges of the latter. The change in the state of the bits of the second divider 7 frequency at the second input occurs on the leading edges of the pulses from the output of the code recording gate 8.

Thus, after the end of the pulse at the output of the prohibition block 4 and the synchronous pulse at the output of the master oscillator 1, the trigger 5 is switched and the divider 3 frequency code is increased by one compared to what it contained at the moment the code was recorded in the second frequency divider 7. Therefore, after switching the trigger 5, in the bits of the second frequency divider 7, the recorded code, the additional code, remains in the bits of the divider 3 frequencies.

Subsequent pulses of the master oscillator 1 pass through the open additional element 6 to the input of the second frequency divider 7. Back front output

the pulse of the second divider 7 frequency trigger 5 switches to one state, opening element 2 and blocking additional element AND 6. At the same time, all bits of the second frequency divider 7 remain in

the zero state, and the pulses of the master oscillator 1 begin to pass to the input of the divider frequency 3. The next input phasing pulse is fed to the input of the prohibition unit 4 in phase with the output pulse of the frequency divider 3 and the device continues to work as described above.

Thus, the introduction of the second frequency divider 7 together with the code recording gate 8 and the additional element 6

ensures reliable operation of the device at any value of the error angle between the input phasing pulses and the output pulses of the divider frequency 3. At the same time, a minimum phasing time is provided which does not exceed the value of the follow-up period of the input phasing pulses.

Claims (1)

Invention Formula A phasing device containing a series-connected master oscillator, an AND element, a frequency divider, an inhibitor unit and a trigger whose output is connected to another input of an AND element, characterized in that, in order to increase the phasing speed, a code recording gate is inserted between the master oscillator output and the second input of the trigger is a series-connected additional element And and a second frequency divider, another input of which is connected to the output of the code recording valve, the first and second inputs of which are connected accordingly But to the other output of the divider and the output of the prohibition block, and the second output of the trigger is connected to another input of the additional element I. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 536609, cl. H 04 L 7/00, published 05.27.75.