SU1615741A1 - Systolic processor of discrete fourier transform - Google Patents

Abstract

The invention relates to computing and can be used in specialized systems of multi-channel signal processing and in measuring and computing systems. The purpose of the invention is to expand the scope of application due to multi-channel data processing. The goal is achieved due to the fact that the device includes a switch 1, an operation unit 2, a permanent memory unit 3, a group 4 of K-1 / K - a size of a transformation / operational units 5, a permanent memory unit 6, group 7 of K storage units 8, switch 10 and control unit 11. 6 sludge.

Description

3161574

The invention relates to computing technology and can be used in specialized systems of multichannel signal processing and in measuring and computing systems.

The purpose of the invention is to expand the scope of application due to multi-channel data processing.

Fig, 1 shows the functional diagram of the (multichannel) systolic DFT processor; in fig. 2 - functional diagram of the operative block; Fig. 3 is functional, with a storage unit diagram; in fig. 4 is a functional diagram of the storage unit switch; FIG. 5 is a functional diagram of the control unit j in FIG. 6 is a functional diagram of the second counter-encoder of the counter states.

The processor (FIG. 1) contains (input M-channel) switch 1, operation unit 2, block 3 of constant memory of weighting factors), systolic matrix 4 of (Nl) -ro operation unit 5, block 6 fixed memory. (weighting factors), group 7 of N storage units 8, output 9 of group 7, (V-code M-channel) switch 10, control unit 11, control unit output 12, first- and second 14 control outputs of the control unit, address output 15 of the control unit and clock input 16.35

The operational processor unit (Fig. 2) contains the first 17, second, 18 and third 19 inputs, the register (weighting factors) 20, the clock input 21, the multiplier 22, the adder 23, the first 24, the second 25 and the third 26 outputs.

Each storage unit 8 (FIG. 3) contains inputs 27 and 28, switch 29, clock input 30, input 31, delay element 32, output 33, nodes 34 and 35 of the registers from (M-1) and | M registers 36 respectively and exits 37 and 38.

Switch 29 (Fig. 4) contains the first 39 and second 40 data inputs, input 41, control input 42, And 43–45 elements, IL 46, per 47, 47, and second 48 outputs.

thirty

40

45

The control unit 11 (FIG. 5) contains a clock pulse generator 49 lo gj, NM-bit binary counter 50, a first decoder 51 of the counter states and a second decoder 52.

. „

with n

5 5

0

0

five

14

The second decoder 52 of the control unit (Fig. 6) contains 1о§2 (Н-1) M-th element OR 53, log N-input element OR 54, element NOT 55, element AND 56, outputs 57 and 58.

The processor works as follows.

Block 3 weighed: their multipliers with a capacity of words has a paged organizer of 1 page of N pages with M words. Each page of block 3 contains weighting factors for data samples with numbers xj |, where i e 1, M, and K is the sequence number of the page. To access block 3 by address output

2

five

15, block 11 is transmitted (log, N + 1O§2 M) -diff address.

Block 6 of the weight factors has a capacity of N words, to access it, you need a logg N-bit address, which is achieved by connecting the higher logg N bits of the address output 16 of block 12 to the address input of this block.

Before the processor starts operation, the counter 50 is reset to zero, and thus the control inputs 41 and 42 of the switches 29 of all blocks 8 receive control signals that zero all registers 36 of all sections 34 and 35 of memory — of the FIFO type.

Let M input parallel data streams be formed in such a way that during the queue M time ticks to the processor input one data sample per each tact, while successively M data samples X from each of the MS data channels (€ T, ll), where n 50, N-1, the number of reference data, - N - the length of the input: - sequence (number of samples). data and i is the data channel number

Samples of data x; (Vi-C l, M; K € G1, N) arrive at the inputs of the input M-channel switch 1, -the control of which input is connected to the output of the first decoder 51 states of the counter 50. As a result, on the 1st clock , bots (1 ik, i ei,. MF K 61, N) The K-Y data readout from the i-th channel is transferred from the input of the switch 1 to its output and then to the first input of the operational unit: 2.

The second input of block 2 comes from the output of block 3 of the weighing factors j of the window weight function.

at the same pace and synchronized with the readings of data x.

Block 2 implements the operations of the form

exit i k)

M

out ,, (1)

ch

k-i

however, the current amount of the form

mil

im

xCO; in expression (1) accumulates in the first block 8 of group 7. Meaning

X

out

transmits further to the first input

systolic matrix 4, the second input of which receives weight factors exp (-J 2 (K-1) / N), where K € 1, N from block 6 are weighting coefficients. The counts W; come on

input systolic matrix 4 at the same tempo and synchronously with the x readings

In block 5 of the systolic matrix 4 with the number 1 (fiei, N-1) and the associated block 8 with the number (1 + 1), the functions are implemented

M

N

wkx w

out (; hz-to -) w J, ...) w j f

1 time

out +

k-l

Z

m

-I

E: (im W;

Xm

N N

.. 1 time. (2)

The current value of the sum in the expression (2) is accumulated in block 8 with the number 1 + 1. There samk. block 2, block 5 of the systolic matrix 4 and associated with them

 blocks 8 of group 7 implement in aggregate the calculation of a one-dimensional DFT with

 pre-weighing the readings of the initial discharge data

N

"

(k-oh

; K-0Z; KM. (3)

This load is calculated in a processor in 2 (N-1) M cycles. Moreover, during the first (N-1) M + l-l3 cycles in the second section 35 of the node 157416

Line of block 8 with number 1 (VI € 1, N). the current sum is accumulated in accordance with expressions (1) and (2), during the entire given period of time from the second control output 14 of the control unit 11, the control inputs of the switch 29 of block 8 with the number 1

0 yr y, 1, y o, formed by the second decoder 52 states of the control unit counter 50 (since Ct (N-1) M during the first (N-1) M operation cycles),

(5 -.Data from the first input 27 of the 1st unit 8 is fed to the second output of the switch 29 and from it to the input of the second section of the node 35, which is connected to the input of the first register 36 of this section SIR. partial sums in expressions (1) and (2) are sequentially rewritten from register to register of the given second 35, from the output of the last register 36

25 of this node arrive at the first exit, 37 of block 8, and further on, the third input 19 of the corresponding block 5 of the system. Tolic matrix 4 (with 1 b 2) or to the third input 19 of block 2 (with)

30 L

I during the following K processor cycles in the block in the block: 5 with the number (1-1) (VI 62, N) of the systolic matrix 4 are formed and the end results are generated in accordance with expressions (1) and (2). Each result comes here already in the first section of the node 34 of the corresponding 1 block 8, since at the (N-I) M-M cycle

4Q of operation by the second descriptor 52 of the counter 50, control signals are generated at O and y 1, which are stored until step 1 III from the beginning of data processing k, f in the processor. Wherein

5, the data arriving at the first input 27 of the unit 8 via the switch 29 is received at its first output connected to the input of the first section of the node 34. Since each block 5 is turned on

0 into the operation with a clock later, then through (M-1) cycles from the beginning of the switching of sections, the first section of the first block tJ. 34 is filled, after the M blocks of the second block 8, and so on up to block 8 with 5 number No Second sections of the node The 35 blocks 8 are then disconnected from the inputs of the block, and the contents of the registers 36 of the second sections of the node 35 are zeroed over this period.

Starting from the M (N-1) cycle, i.e., “on the | Mth cycle after switching sections | of nodes 34 and 35, the first block 8 outputs the results С i- from the second output 38 of this block 8, -; which takes M clocks Выв Output (counts C.; o from the second output 38 of the first block 8 arrives at the output 9 of the group of blocks 8 and from there at the output of the output M of the channel switch 10 further into the output data channels. The output M-channel switch) It is also mismatched with control signals: slash from the first decoder 51 C. a scale of 50, which is an unc-arnial M-bit code, as a result, at every 1st clock (1 i - n + W where i € 1, M, n e1, N) is the countdown

ata c || is transmitted to the i-th output anal.

At the cycle (M + 1) from the beginning of the output d; data, the switch 29 of the first unit 8 of group 7 connects to the second input: 8 of this unit 8 the second output 38 of the iToporo unit 8. This is accomplished by listening to the control inputs 41 p 42 of the switch-control Y - V2 O signals generated by this Ny moment by the decoder 36. With this set of control signals y k y data, they are fed to the second input 42 of the switch 29 and from its first latch 47 to the input of the first section of the node 34. At the same time the data from the first input 27 of block 8 (i.e. from the so-called output of block 26) comes nr first input of the switch 29, the first - .gr 8is unit 48 outputs its second input of the second node N 35.

: At the cycle (M + 1) from the beginning of the data output, similar switching operations are carried out in block 1 8, in which the third output 26 of block 5 is connected again; switch 5 is connected to the input of the second evil 35, and input the first node 34 in this block: K (it turns out to be connected to the second; | g output 38 of the next (1h-1) -th bioca 8 (VI 6 2, N-1),

Thus, during the next MI cycles, counting from the beginning of the output of the results, the output is performed (fex of the generated results C i.; The node nodes 34 of all blocks 8 at tOM are sequentially under 11 values one after the other, forming a single FIFO memory capacitive z, N (M-1) registers.

20

25

thirty

35

40

45

50

55

in the second nodes 35, the current sums are gradually accumulated in accordance with the statements (1) and (2) for re-raising; those who follow the X, j4 data sequence across all input channels, thus there are no data input / output pauses in such a multichannel processor.

Claims (1)

Invention Formula . 20 25 thirty 35 0 five 0 five The systolic discrete Fourier transform processor containing a control unit and K-1 (where K is the size of the transformation) of operadion blocks, with the first and second outputs of the K-th (1j K-2) of the operational block being connected respectively to the first and to the second information inputs (K +, fD-ro of the operadone block, the clock inputs of all operational blocks are pushed to the clock cycles of the output of the control unit, the clock input of which is connected to the clock input of the processor, while the operating unit contains the adder multiplier and register, which output It is connected to the first multiplier input, the output of which is connected to the first / information input of the adder and is the first output of the operative unit, the second output, which is the registration output of the clock input which is connected to the clock & input multiplier 1I is the clock input operating unit, the first and second informational inputs of which are, respectively, the second information input of the multiplier and the information input of the register, denounced by the fact that, in order to expand the scope of application by multi-channel data processing, 3 of them are two blocks of constant memory, two switches, the K-th operational block of K storage blocks, with the first output and the first information input of the p-th (, K-i) block storage is connected to the control input and the second output (p + 1) of the storage unit, the third output of the K-th (Ifc1, K) of the operation unit is connected to the second information input of the storage unit, the third output of which is connected to the third information input the input of the operating unit, the first control - U1DIY. the output of the control unit connected to the control inputs of the first and The second switch, the output of the first j switch is connected to the first information input of the K-th operation unit, the first output of which is connected to the first information input of the first operation block, the second control output of the control unit is connected to the control input of the first storage unit, the second output of which is connected to the information input of the second switch, the outputs of the group of which are the information outputs of the processor group, index 5741 the stroke of the control unit is connected to the clock inputs of all the storage units and the i control inputs of reading the first and second blocks of the constant memory, the storage unit containing two register nodes, a delay element and a switch, the first and second outputs of which are connected to the information inputs of the first and second nodes of the registers, respectively, the clock inputs of which are interconnected and are the clock input of the storage unit, the first, second and third outputs Formational inputs of the group of which are the outputs respectively of the information inputs of the primary switchboard, the output address of the control unit is connected to the address inputs of the first and second fixed memory blocks, the outputs of which are connected to the second information inputs of the K-th and first 20 but the delay element, the first and second delay nodes, the control input of the switch is connected to the input of the delay element and is the control input of the storage unit, the first and second information inputs of which are respectively the first and second inputs of the switch. Operating blocks and clock you fig, g Secondly, the outputs are respectively but the delay element, the first and second delay nodes, the control input of the switch is connected to the input of the delay element and is the control input of the storage unit, the first and second information inputs of which are respectively the first and second inputs of the switch. J / Fy Fig.Z 51 0 /five 9 - 72 of FIG. five g / g5 Compiled by A. Baranov Editor A. Kozoriz Tehred L, Serdyukova Proof-jyj Ujypojjm Order 3989 Circulation 567 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR  113035, Moscow, Zh-35, Raushsk nab. 4/5      , C-, I - -.-.- I I Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 ; j 50 52 F 5Z " 5J jd 55 ± P  I 54 Subscription