SU1319045A1 - Device for calculating convolution - Google Patents

Abstract

The invention relates to computing and can be used in the construction of specialized computing systems operating in real time. The purpose of the invention is to simplify the device. This goal is achieved due to the fact that the device includes K L computing blocks 1.1-1.KL, a block of registers 2 and L of switches 3.1-3.L, each computing block contains two buffer registers, a coefficient register, a multiplier, result register and adder. The decrease in the equipment volume is due to the fact that due to the rational organization of the computational process in the device, there is no need to use L - 1 delay lines of length N - K cells each. 2 pcs. a (L with so about 4 SP

Description

t

The invention relates to computing technology and can be used in the construction of specialized computing systems operating in real time.

The purpose of the invention is to simplify the device.

Fig, 1 shows a diagram of the device; in fig. 2 is a diagram of a computing unit.

The device (Fig. 1) contains KL computing blocks 1.1, 1.2, ... “. . one . KLi.

Each of the computational blocks l.i (FIG. 2) contains a buffer register 4.1, a register 5.1, a register of 6.1 coefficients, a multiplier 7.1, a register 8.1 of the result, an adder 9.1, and a register 10.1 of the result.

When performing a one-dimensional convolution, the device operates as follows. During this operation under the influence of the signal One-dimensional convolution arriving at the control input of the device, the switches 3.1, except for transmitting information coming from the first information output of the computing unit 1, (1-1) K, to the first information input of the computing unit 1 , (1- -1) K + 1, and the switch Z.G- to the first information input of the computing unit 1.1 samples of the input sequence X (1)., X (P), which simultaneously with the signal One-dimensional convolution begin to flow from the output of the main memory 2 at the speed of one countdown per beat.

The basic operations A and B are defined, and by the basic operation it is necessary to mean a repeating set of actions performed by the computing unit.

Basic operation A is performed during one clock cycle in computational unit 1 as follows. At the initial moment of time, an operand is stored in the first buffer register 5.1, which is then fed to the second input of multiplier 7.1, to the first input of which the coefficient 6.1 enters the input of the coefficient 6.1. Q (KL-i + 1). Then the multiplier 7.1 forms the product 63 (K b-1 + 1) a-, which, with the arrival of the clock pulse, is written into the first register 8.1 of the result. Under

190452

the impact of the clock pulse also overwrites the contents of a, the first buffer register 5. (1-1) and the contents of a, the second

5 of register 4.1, respectively, into the second buffer register 4.1 and the first buffer register 5.1 (in the case of block 1.1, a new input from the JO account is written to the second buffer register 4.1).

The basic operation B is executed during one clock cycle in the computing unit 1.1 as follows. At the initial time in

 5 first 9.1 and second 10. (1-1) result registers are stored respectively the product co (K L-i + l) af and the partial result L, -, which are then fed to the inputs of the adder

20 9.1, which forms their sum, With the arrival of the clock pulse, the specified amount is recorded in the second register 10.1 of the result.

Formation countdown output

 sequences with the number p (p 1.2P-K L + 1) are determined by the expression

y (n) co (D) X (n + Dl) + co (Dl) X (n + D-2) + 30 + w (D-2) X (n + D-3) + ,,. + s (1) X (p),

where D K-L.

The input of samples of the input sequence, which are involved in the formation of y (n), begins at the same number n, when the counting X (n) enters the second buffer register 4.1. Then, for the next D-1 clock cycles, the arrival of samples X (n + 1), X (n + 2) X (n + D-1) continues,

40 where each new input count is written to register 4.1, and the previously received samples are shifted by one, the position in the shift register, which is formed by buffer registers 4.1

45 and 5.1. Thus, in the clock cycle n + D, the count X (n + D + l) enters the first buffer register 5.1, and the counts

X (n + D-2), X (n + D-3) X (n) is hidden in the following register positions

50 shear. The formation of the result y (i) begins in the cycle n + D + l, during which the basic operation A is performed in block 1.1, which results in the first register 8.1 of the result

55 is the product of CO (D) X (n + + 0-1). In addition, the count X (n + D-2) is written to register 5.2, the count X (n + D-3) to register 4.3, the count X (n + + D-4) to register 5.3 and t, d

Tact n + D + 2. In block 1.1, the basic operation B is performed, as a result of which the sum y (n) / P + SLE (B) .X (n + B-1) is written to the second result register 10.1 (the first input of the adder 9.1 is always sent to code zero) , and in block 1.2, the basic operation A is performed, as a result of which the result is written to the first register 8.2, the product ω (D-1) X (n + + D-2). In addition, the count X (n + D-3) is written to register 5.3, counting X (n + D + 4) to register 4.4, counting X (n + + D-5) to register 5.4, etc.

Beat n + D + 3. In block 1.2, it performs a basic operation B, as a result of which the sum y (n) y (n), + CO (D-1X (n + D-2)) is written to the second result register 10.2, and

1.3- basic operation A, in the result of which the product CO (D-2) X (n + D-3) is written to the first register 8.3 of the result. In addition, X (n + D-4) is written to register 5.4, X (n + D-5) to 4.5, and so on.

Beat n + d-f4. In block 1.3, the basic operation B is performed, as a result of which the sum y (n) y y (n) (D-2) X (n + D-3) is written to the second result register 10.3, and

1.4- basic operation A, as a result of which the product CO (D-3) X (n + D-4) is written to the first register 8.4 of the result. In addition, the count X (n + D-5) is written in register 4.5, the count X (n + D-6) in the register

5.5 etc.

Tact n + 2D. In block 1.7 (D-1), the basic operation B is performed, as a result of which the sum y (n) d, y (n). O is written to the second register lO. (D-l) of the result. + Co (2) X (n + 1), and in block 1.D the basic operation A, as a result of which the product CO (l) X (h) is written into the first register 8.D of the result.

Beat n + 2D + 1. In block 1.D, the basic operation B is performed, as a result of which the final value y (n) is written to the second register 10.D of the result, from which it enters the main memory 2. When performing a two-dimensional convolution, the device works as follows. During this operation, the coefficient register 6.1, where, the coefficient CO (K-K + 1, 1) is stored. Simultaneously with the signal two-dimensional convolution, which

arrives at the control input of the device, from the output of block 2 of registers to the input of the second buffer register 4 (L-1) K + 1 through switch 3.L (since a two-dimensional convolution signal arrives at its control input at a rate of one sample per clock the X samples (n, t) of the input array that satisfy condition 1: P: ZK-1,. In this case, the indicated samples are transmitted in columns, i.e. in the cycle with the number R (n, m) (mI) (ZK- 1) - (- n to the input of register 4. (L-1) K + 1, the counting X (n, t) is received, which then, with the arrival of each clock pulse, is shifted by one position in the shift register formed by 2L K buffer registers 4 (Ll) K + r., 5. (L-1) KH, 4. (Ll) K + 2, 5. (Ll) K + 2, 4.LK, 5.LK, 4. (L-2) K + 1, 5. (L-2) K + 1, 4. (L-2) Ki-2, 5. (L-2) K + 2, .. ., 4. (L-2) Kf

+ K, 5. (L-2) K + K4.1,5.1, 4.2,

5.2, ..., 4.K, 5.K.

The formation of an arbitrary count y (n, m) of the output array is determined by the expression

to Y (n, t) 2Iu (K, l) X (n + K-l, m) +

1C

+ Zlw (K, 2) X (n + K-l, m + l) + ... +

to 1

+ ZIu (K, L) X (n + K-l, m + L-l) y (n, m)

+ y (nm) + ... + y (n, ra),

where, lsm M-L + 1.

The formation of the counting y (n, iii) begins in time with the number (n + + K-1, m) +2 (L-l) (2L + 3m-4) -m +

+ P + 2, when the input buffer X (n + K-1, t) arrives at the input of the first buffer register 5.1, which, with the arrival of the next clock pulse, is written into the specified register. In the next cycle with the number S + l, in the computing unit 1.1, the basic operation A is performed, as a result of which the product sa (K, 1) X (n + K-1, t) is written to the first register 8.1.

Tact S + 2. In the computing unit 1 .. 1, the basic operation B is performed, as a result of which the sum y (n, t) + ω (K, 1) X (n + K-1, t) is written to the second register 10.1 of the result, and in the computing unit 1.2, the basic operation A, as a result of which in the first register 8.2

the result is the product of y (k-1, 1) x (, t).

Tact S + 3, In the computing unit

1.2 the basic operation B is performed, as a result of which the sum y (n, ra) j y (n, m), ω (K-1), 1) X (n + K-2, is written to the second result register 10.2) t), and in the computing unit 1.3 - basic operation A, as a result of which in the first register JO

8.3 The result is the production of CO (K-2, 1) X (n + K-3 |, t).

The clock stroke S + K + 1, In the computing unit 1, K, the basic operation B is performed, as a result of which in the second 15 register 10, K the result is recorded the sum y (n, t) cnp, t) (n, t) k. + + ω (1, l) X (n, m). In the same clock cycle in the computing unit 1, K + 1, the basic operation A is performed, as a result of which the product L (K, 2) X is written to the first register 8, K - 1 - 1 result (n + K-1, t + one).

The clock cycle S + K + 2. In the computing unit 1.K + 1, the basic operation B is performed, as a result of which the sum (n, t), y (n, m) + nd ( K, 2) h X (n + K-1, t +), and in computing unit 1, K + 2 the basic operation A, in the 30 result of which the product w is written to the first register 8. K + 2 of the result (Kl, 2) X (n + K-2, tp + 1).

The beat S + K + 3, In block 1. K + 2, the basic operation B is performed, as a result of which the sum y (n, t) y (n, m) + w is written to the second register 10, K - 2. (Kl, 2) X (m-bK-2s m + 1), and in block 1.K + 3 - basic operation A,

Record 8. (L-1) K result is written as the product from (K, L) X (, m + L-1).

The clock S + (Ll) K + 2, In block 1, (L-1) "5, the basic operation B is performed, as a result of which the sum of y (m, n is written to the second register 10, (L-1) K + 1) ), y (n, t) - - + y (K, L) X (, mtL-1), and in block 1, (Ll) K + 2, basic operation A is implemented, resulting in the first register 8. ( Ll) K + 2 result is written as the product of co (Cn, K) to X (t + K-2), m + L-1),

The clock. In the computing unit l.K L, the basic operation B is performed, as a result of which the final value y (n, t) is written to the second register 10.K-L, from which the next clock enters the information input of the register 2 block. The operation of the device proceeds in the same way, when processing 25 of those samples of the input array X (n, m), which satisfy the condition

2 (h-l) fen 6 (2h4-l) K-l,

where h. 2.3, ..

Claims (1)

Invention Formula 20 35 A device for calculating a convolution containing a block of registers, L switches and L groups of computational blocks of K blocks each (K-L is the length of a sequence of coefficients), with the output of the block of registers connected to the first information inputs as a result of which, in the first register, 40 pvogo and L-ro switches, with 8, K + 3 results being written, each computational unit contains the first and second result registers, the adder, the multiplier, the first and second buffer registers and the coefficient register of the capital, the output of which is connected to the input of the multiplier, the output of which is connected to the information input of the first result register, the output of which is connected to the first input of the sum50 .InputW (K-2,2) X (n + K-3, t + 1). The beat S-S-2K + 1, In block 1.2K, the basic operation B is realized, as a result in which the sum y (n, y (n5 ha), + y (n, m) y (n, m); 1 + + co (1, 2) x (n, m + 1 ). Clock S + (L-l) K + lt In the computing unit 1, (L-1) K, the basic operation B is performed, as a result of which in the second register 10, (L-l) K the result the torus, the output of which is connected to the information input of the second result register, the second input of the multiplier is connected to the output of the first buffer register, the information input the sum of y (n, ha) y (n, t) + is recorded, - which is connected to the output of the second + y (t, n) +,,, + y n, t). At the same time in calculator 1, (L- -1) K + 1, the basic operation A is performed, which results in the first rebuffer register, outputs of the first buffer register and the second register of the K-th (, K-1) result of the computing unit of the 1st (1 1, L) JO 15 190456 Record 8. (L-1) K result is written as the product from (K, L) X (, m + L-1). The clock S + (Ll) K + 2, In block 1, (L-1) "5, the basic operation B is performed, as a result of which the sum y (m, n is written to the second register 10, (L-1) K + 1) ), y (n, t) - - + y (K, L) X (, mtL-1), and in block 1, (Ll) K + 2, basic operation A is implemented, resulting in the first register 8. ( Ll) K + 2 result is written as the product of co (Cn, K) to X (t + K-2), m + L-1), The clock. In the computing unit l.K L, the basic operation B is performed, as a result of which the final value y (n, t) is written to the second register 10.K-L, from which the next clock enters the information input of the register 2 block. The operation of the device proceeds in the same way when processing those samples of the input array X (n, m) that satisfy the condition 2 (h-l) fen 6 (2h4-l) K-l, where h. 2.3, .. Invention Formula the torus, the output of which is connected to the information input of the second result register, the second input of the multiplier is connected to the output of the first buffer register, the information input which is connected to the output of the second the buffer register, the outputs of the first buffer register and the second register of the K-th (, K-1) result of the computing block 1st (1 1, L) 713 the groups are connected respectively to the information input of the second buffer register and the second input of the adder (K + 1) -th computing unit of the 1st group, the outputs of the first buffer register and the second register of the result of the K-th computing unit M-th (, L-1) group connected respectively to the first information input of the (M + 1) switch and the second input of the adder, the first computing unit (M + 1) -th group, the output of the second register of the result of the K-th vocal section of the L-th group of the sub 58 the keys to the information input of the register unit, the output of the 1st switch is connected to the information input of the second buffer register of the first computing unit of the 1st group, and the control inputs of all the switches are interconnected and are the input of the device operation mode, characterized by that, in order to simplify the device, the output of the first buffer register of the K-th computing unit (t + 1) -th group is connected to the second information input of the M-th switch. r2 Compiled by A, Baranov Editor N. Rogulich Tehred I., Popovich Proofreader T, Order 2514/44 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries P3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4