SU1361574A1 - Fourier digital transform processor - Google Patents

Abstract

The invention relates to specialized digital computational techniques: computers designed to perform a discrete Fourier transform procedure, and can be used in real-time digital signal processing systems. The purpose of the invention is to increase speed. This goal is achieved due to the fact that the processor includes a block of L-point discrete Fourier transform 1, an output block 2, a doubling unit 3, an interpolator 4, a delay element 5, a subtractor 6, a delay element 7, and an adder 8. 2 or .

Description

The invention relates to specialized digital computing tools for performing the Discrete Fourier Transform (DFT) procedure and can be used in real-time digital signal processing systems.

The aim of the invention is to increase speed.

Figure 1 presents the scheme of the processor; 2 shows time diagrams of his work.

The discrete Fourier transform processor (Fig. 1) contains an L-point discrete Fourier transform (DFT) unit 1, an output unit 2, doubling (spectral resolution) 3.1-ZM nodes, each of which contains an interdolator 4, a delay element 5, subtractor 6, delay element 7 and adder 8.

The device works as follows.

An input array of L complex samples of the 1st segment of the analyzed signal is parallelly fed during the time interval 0- (Ь-1) D to the input of block 1. Then, during the time interval b- (2L-1) d, to the input of block 1 the array from L samples of the 2nd segment, etc.

Such a dynamic update of the input array can be accomplished, for example, by turning on the input block 1 of a buffer storage device (memory) that has an input switch, two multi-bit shift registers and an output switch. The input switch connects to the input of the buffer memory input 1-gr (2nd) of the shift register when applying a control pulse to its 1st (respectively 2nd) control input. The output switch connects the output of the 1st (2nd) shift register to the output of the buffer memory when applying a control pulse to its 1st and (respectively 2nd) control input. The differently named control inputs of the switches are pairwise combined and form the 1st and 2nd control inputs of the buffer memory. The clock inputs (shift) of the 1st and 2nd shift registers are respectively the 3rd and 4th clock inputs of the buffer memory. From the moment of switching on, the input switch for L operation cycles connects the input of the 1st shift register to the input of the buffer memory, which performs the function of the 1st delay line with taps during this period of time (the input of the register means the input bus of the sequential code every time the code sequence of processed samples). On completion (L-l) -ro

cycle is connected by the output switch for a period of time B d - (2L-1) & the output bus of the parallel code of the 1st shift register (in each, bit), i.e. taps 1st

delay lines to the vector input of block 1; at the same time, for the specified period of time, the 1st register performs i as a combination of L multi-digit storage registers, and the input

the switch connects to the input of the buffer memory of the input of the 2nd shift register, for this period of time it performs the function of the 2nd delay line with taps. So

Thus, by alternately changing the functions of the two registers, alternating input and output of block 1 of the arrays of the input samples is provided. In the process of functioning of the buffer

The charger is used to supply clock pulses with a frequency to the ultrasonic input of that of the shift registers, which in this phase of the work serves as a delay line with taps.

The principle of the processor is as follows. Let, for example, M 8 and Ng N L.-M. In this case, all spectral resolution doubling nodes operate in a jumping mode. AT

time t, at the input of unit 1, a set of samplers of the 1st segment of the signal being processed is fed. At time t, the output of block 1 forms-: the results of the DFT of the 1st input run

array. At the moment t-at the output of block 1, the DFT results of the 1st input array are formed. At time t, the output of the interpolator 4 generates the LP interpolated coefficients.

Be, corresponding to the L-point decomposition of the input signal into harmonic components, whose frequencies are located in the middle of the frequency intervals between the frequencies corresponding to the DFT coefficients A ,.

Harmonic components corresponding to the DFT (A expj -----) have LJ

H5T periods that fit exactly K (integer) times on the decomposition interval of L points. Therefore, the summation of the values of A and A is equivalent to the spectral decomposition of the input signal over components of the form Kp

exp;

2L

where K is even. Harmonic components, the decomposition of which gives the values of Be, respectively

27 (K +0.5) are used for the frequencies expj--

periods of which over an interval of L points are laid K + 0.5 times (i.e. they end at the end of the interval with phase 1). Consequently, for the phase matching of the basis decomposition functions corresponding to the BP coefficients, it is necessary to rotate the phase of the coefficient B .g | with respect to the phase of coefficient B on TG, which is realized by subtracting in subtractor 6. From what has been said, it follows that to simulate doubling the number of decomposition points, it is necessary to realize vectorial addition of arrays of numbers A and A,., and subtracting arrays of numbers Bg, and B j, received over adjacent (non-overlapping) in time segments of the input signal. As a result, we obtain a decomposition of the signal into components

7Kp

type A

exp

t2L

where when

K.P.

the even results are taken from the output of the subtractor 6, and for odd results, from the output of the adder 8.

When repeating a similar iteration of doubling the number of decomposition points in node 3.2, it is necessary to take into account that for this block the input array corresponds to the decomposition by an interval of 2L points, i.e. in node 3.2, in the jumping mode, all operations can be performed 2 times less frequently than in block 1, but the dimensions of the input and output arrays are 2L and 4Lp, respectively, i.e. 2 times the dimensions of the arrays at the input and output of the node 3.1. Each node Z.K differs from node Z.K-1 by slowing down (when operating in the jumping mode) by 2 times the rate of arrival of the input array and increasing by 2 times its dimension. By jumping, we understand this mode of operation of the node ZK, when blocks 8 and 6 in it are working off their functions once in two periods.

update information at the input of this cascade (i.e., subtractor 6 realizes vector subtraction of the array obtained at the odd step of updating the array at the input of this stage obtained at the previous even update step; similarly, adder 8 implements vector summation).

If it is necessary to implement a spectral analysis with an update on N N / 2 points, the last doubling node K Ct works in a sliding mode. In the latter case, blocks 8 and 6 in this cascade fulfill their functions once for each update period of information at the input of this cascade. If necessary, updates on Cd N / 4 in the sliding mode work the last and the penultimate nodes. and ЗК „,, (note 8 is nodes 3.3 and 3.2). At Np N / 2, this mode differs from the existing one in that the rate of array update at the output of node 3.2 coincides with the rate of array update at its input (i.e; the rate does not decrease by 2 times does not occur which entails double load on the node 3.3.

Claims (1)

Invention Formula A discrete Fourier transform processor containing an L-TO non-continuous discrete Fourier transform unit and an output block whose output is an information output of a processor whose information input is an information input of an L-point discrete Fourier transform block whose output is connected to the output of the output block characterized in that, in order to increase speed, the output block contains (M N / L, N is the size of the input sequence being processed) of the doubling nodes, and the output i-ro (i 1, M-1) of the node y The unit is connected to the input (i + l) -ro of the doubling node, the output of the Mth doubling node is the output of the output block, the output of which is the input of the first doubling node, the jth (J Y, M) node doubling contains an adder, a subtractor, two delay elements and an interpolator whose course is connected to information the first input of the first delay element, the first and second outputs of which are connected respectively to the first and second inputs of the adder, the output of which is connected through the installation OR to the output of the subtractor and is the output of the doubling unit, the input of which is interconnected G1 P n n n P P Jrl Editor V. Bugrenkova Compiled by A. Baranov Tehred A. Kravchzts Proofreader O. Kravtsova Order 6292/49 Circulation 671 Subscription VShPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 15746 the interpolator and the information input of the second delay element, the first and second outputs of which are connected respectively to the first and second inputs of the subtractor, and the clock inputs of the first and second delay elements are interconnected and are the J-M clock input of the processor. P P P- P P n t Jl P yy G1 P rLt Phage. 2