SU1141420A1 - Device for implementing fast walsh transformation - Google Patents

Abstract

An apparatus for performing Fast Walsh Transform, comprising first and second switches, an adder-subtracter and a memory unit, wherein the first information and the control inputs of the first switch are respectively information and synchronizing device inputs, characterized in that, in order povsheni speed, in it has four registers, a comparison unit, a constant memory block, the first and second counters, a one-shot and clock generator, the output of which is connected to the counting input of the first A sensor whose output is connected to the address input of a permanent memory unit, the output of which is connected to the first input of the comparison unit to the information inputs of the first and second registers, the outputs of which are connected respectively to the first and second information inputs of the second switch, the output of which is connected to the address input a memory unit whose output is connected to the information inputs of the third and fourth registers, the outputs of which are connected respectively to the second and third information inputs of the first comm commutator the first and second outputs of which are connected respectively to the first and second inputs of the adder-subtractor, the code of which is connected to the information input of the memory unit, the control input of the second switch is connected to the second input of the comparator unit and connected to the output of the second counter, the counting input of which is connected to the output of the one-shot, the input of which is the start-up input of the device, and the output of the comparator unit is connected to the control input of the clock generator.

Description

1 The invention relates to automation and computer technology and can also be used on digital signal processing equipment for low-frequency signals (for spectral analysis and synthesis, digital filtering, etc. A Walsh-Hadamard device for orthogonal transformation of digital signals is known. totalizers-subtractors with 2 totalizers-subtractors in each group and devices containing 2 totalizers-subtractors, 2 registers, 2 blocks of OR elements and 2 blocks of AND elements, and a block of formation of intervals, and The device input (1 1 + 2) is connected to the information input (2i-1) -ro of the AND element block, the output of the i th adder of the a-subtractor is connected to the information input of the AND block, the control inputs of the AND elements with numbers ( 2i-1) and 2 | are connected respectively to the direct and inverse inputs of the block of formation of time intervals, the outputs (2J-1) of the th and 2j-th blocks of the elements AND through the block of the elements OR are connected to the input of the {-th register, the outputs (2 | -1) -th and 2j-ro registers (connected to the inputs of the j-th and (+2) th adders-subtractors, the outputs of the register are outputs oystva l. The drawbacks of the device are its complexity and large hardware costs for implementation, since the device contains 2 channels of the same type, and the hardware costs increase with P. In addition, information processing does not occur as soon as the values of the tested source are updated, but only after arrival and recording all samples x, - into the device registers and further the signal values are processed in At iterations, this leads to a delay in the appearance of the desired coefficients at the device output and therefore. to reduce the overall processing speed. The closest in technical terms to the invention is a device for performing a fast Walsh transform (BCP), containing 2 totalizers-subtractors and 2 register RAMs (volume L words each), with the inputs of the first and you 20 moves of the second totalizer-subtractors connected to the corresponding inputs the first register RAM intended for storing the input data, and the inputs of the second and the outputs of the first adder-viewers are connected to the corresponding outputs of the second register RAM intended for storing the full-time results. To prepare for the processing of the next vector, buffer RAM can be used, and instead of two adders-subtractors, the first sum of the torch and switching circuits connected to the corresponding inputs-outputs of the register RAM. In a known device, the information is sequentially inputted to the input register RAM and then to the first adder-subtracter, in which the sum and difference of the consecutive incoming pairs of samples are calculated, and the results are recorded into the second register RAM, which is used to store intermediate results that are initial at the next iteration . Only after the input register is filled and the sum and difference of the last pair of samples is received, does the information transfer through the second adder-subtractor into the empty register, i.e. move to the next iteration, etc. The pauses between the arrival of samples are not used for computations. The disadvantages of such a device are low speed, since all you need to do is n log2N conversion steps, consider all RAM (N words) and N words to be copied from the buffer RAM, i.e. the total number of one-. walkie-talkies will be NXl + log N) and a large memory, since 3 RAMs with N words each are required. The purpose of the invention is to increase the speed of the device (by actively using the pauses between the arrival of samples of the signal under study for calculations). The goal is achieved by the fact that in the device containing the first and second switches, the totalizer and the memory block, the reception of the first information and control inputs of the first switch are respectively the information and synchronization inputs of the device, four registers are added to the comparison block, the block a fixed memory, the first and second counters, a single vibrator and a clock pulse generator, the output of which is connected to the counting input of the first counter, the output of which is connected to the address input of the fixed memory unit, The output of which is a pvdclock to the first input of the comparison unit and to the information inputs of the first and second registers, the outputs of which are connected to the first and second informational inputs of the second switch, the output of which is connected to the address input of the memory block whose output is connected to the informationHHbw the inputs of the third and fourth registers, the outputs of which are connected respectively to the second and third information inputs of the first switch, the first and second outputs of which are connected respectively to the first and second At the inputs of the adder-subtractor, the output of which is connected to the information input of the memory block, the control input of the second switch is connected to the second input of the comparator unit and connected to the output of the second counter, the counting input of which is connected to the start input device, and the output of the comparator is connected to the control input of the clock generator. FIG. 1 shows the block diagram of the device in FIG. 2 — a graph of the conversion for p. 4. The device contains a generator of 1 clock pulses, a single vibrator 2, a counter 3 (in 2 states), a counter 4 (nap2 SOS-UNI), block 5 memory, block 6 comparisons, registers 7 and 8, switch 9, Elok 10 memory (RAM for N words), registers 11 and 12, switch 13, adder 14, and 2 values of the discrete input signal are processed sequentially as they arrive, the sum and difference of each pair of samples being written in place of the same numbers in block 10. The sequence vtolneni -vychitani summing operation unit 5 is set so that in the pauses between the arrival of further processing samples already produced intermediate results obtained in following iterations, in accordance with a conversion graph (Figure 2). Thus, by the time of the arrival of the last sample, most of the required number of operations will be completed (in Figure 2, this part is outlined with a dotted line and highlighted). To obtain the final result, it will remain to perform 2 (2 -1) operations instead of (p-1) 2, as in the known device (without taking into account the operations associated with the use of the buffer RAM). In this case, the increase in speed will be greater than / / 3 times, where h is the order of conversion. Saving memory is achieved due to the fact that instead of two RAM for N words each, one RAM is used for N words and four registers 7, 8, 11 and 12 or RAM for four words for intermediate storage of the terms and their addresses (for the time being nor add-read operations). The memory will be reduced 2 / (1 + 4 / N) times, i.e. for most N, a saving of memory is almost doubled. The device works as follows. The information input device sequentially receives 2 numerical values (samples) of the investigated discrete signal. At the moment of arrival of the first sample, a ready signal appears on the device input and a one-shot 2 is triggered, which starts counter 3. At the output of counter 3, an address code appears. Ca, in which a block X (0) is recorded in block 10. After the arrival of the second sample at the output of the counter 3, the address code of the next cell appears in block 10, etc. Thus, counter 3 sequentially distributes the addresses of the cells of block 10 into which samples are written and carries information about the number of incoming samples. After the sampling recording process has been completed, block 10 includes a generator 1, which starts counter 4 and block 5, at the output of which the addresses of the cells of block 10 appear, above which you need to perform an add-subtract operation. S1 Addresses of the first and second addends (subtracts) are remembered for the duration of the operation in registers 7 and, respectively, and the numerical values of addends extracted from block 10 are in registers 11 and 12. After the sum-subtrade operation is performed in the adder 14, the result of two The numbers are written to block 10 at the address of the first number, which is stored in register 7, and the result of the subtraction is written to the address of the second number stored in register 8, then the output of block 5 contains the addresses of the new pair of terms, and the next step transform nor etc. So that the circuit does not go deeper into block 10, where no samples have been recorded yet, block 6 is entered into the device, not the input, which receives information about the addresses from the output of block 5 and counter 3. If the addresses at the inputs of block 6 are equal, the output a signal appears that stops generator 1, and the block waits for the next sample to arrive. With the arrival of a sample, a signal appears on the input, which again tilts the one-shot 2, the state of counter 3 increases by one, and the switch 9 connects the outputs of this counter to the address input of the block 10, the process of recording the new sample present on the information input and fed through switch 13 to the appropriate cell of block 10, after which the odibOOO17000 2000 18 010 3001019 О О О 4001120 О 1 О

21О О 1О37

22О 1 1О38

23О О 1139

24O 1 1140

90100 25 1 O O O O 41 1 O O O 57 O 1 O O

10О 1О 1

11O 11 O

12O 11 1

13О 1О О

14 a 1 10

15 about 1 about 1 160111

Such a sequence of binary numbers can easily be formulated10053O O1O

110541 O.1O .10155O O11

111561 O11

With the help of four multiplexers connected to the second counter 4 06, the novibrator 2 recovers its state, generator 1 is turned on, and a new stage of computation begins. The peculiarity of the device operation is that in the pauses between the arrival of the samples it is possible to process the already obtained intermediate results at the following iterations. This possibility of going through the iterations is provided by a certain sequence of the formation of the addresses of the terms, which is determined by block 5 of a constant step. The addresses at the output of block 5 appear in the following sequence (for this sequence it is easily obtained from the transformation graph shown in Fig. 2): 0,1,2,3, 0,2,1,3, 1- iteration 2 - iteration 4,5,6,7 4,6,5,7, - 0,4,1,5,2,6,3,7 1- ite-2- itte-3- iteration of the ratio of 8.9,10, 11, 8,10,9,11 1-ita-. 2-iteration 12,13,14,15 12,14,13,15, 1- itera- 2- iteration 8,19,9,13,10,14,11,15 3- iteration 0,8,1 , 9,2,10,3,11,4,12,5,13,6,14,7,15 4-iteration These RAM addresses at the output of block 5 must be obtained in binary representation, i.e. in the following form: 1 1 О О 49 О О О О 1 1 1 1 50 1 О О About 51О О О 1 52О О О 1 7. on n-2 states (on 64 states for). At the end of the calculations, the resulting values of the Walsh transform coefficients are recorded in the cells of block 10. Thus, the proposed device allows one to increase rapidly 208 the effect of filling the control unit by actively using pauses between samples to continue the calculations by и and / 3 times, where n log2N is the order of conversion, and reduce the memory size by almost two times (for large N ), and the gain is greater, the larger the size of the input vector.

ig.1

CW (D)

Claims (1)

A DEVICE FOR PERFORMING A WALSH FAST CONVERSION, comprising the first and second switches, an adder-subtractor and a memory unit, the first information and control inputs of the first switch being respectively information and synchronizing inputs of the device, characterized in that, in order to improve performance, four register, comparison unit, read-only memory, first and second counters, one-shot and clock generator, the output of which is connected to the counting input of the first counter whose output is connected to the address input of the read-only memory block, the output of which is connected to the first input of the comparison unit and to the information inputs of the first and second registers, the outputs of which are connected respectively to the first and second information inputs of the second switch, the output of which is connected to the address input of the memory unit the output of which is connected to the information inputs of the third and fourth registers, the outputs of which are connected respectively to the second 5 'and third information inputs of the first switch, the first the second and second outputs of which are connected respectively to the first and second inputs of the adder-subtracter, the output of which is connected to the information input of the memory unit, the control input of the second switch is connected to the second input of the comparison unit and connected to the output of the second counter, the counting input of which is connected to the output one-shot, the input of which is the input of the start of the device, and the output of the comparison unit is connected to the control input of the clock generator. 1 1141420