SU1746390A1 - Device for defining image attributes - Google Patents

Abstract

The invention relates to automation and can be used in image processing systems. The purpose of the invention is to increase the speed of the device and expand the scope of application due to the possibility of calculating the moments of higher order. Two counters, a switch, two registers and a group of units for calculating moments are introduced into the device, which makes it possible to replace the multiplication operations with a shift operation by a specified number of bits. 1 hp f-ly. 1 il.

Description

The invention relates to automation and computing and can be used in image processing systems.

The purpose of the invention is to increase the speed of the device and expand the field of application due to the possibility of calculating the moments of the highest orders.

Figure 1 shows the structural diagram of the device.

The device contains a matrix of 1 PVs, analog-to-digital converter 2, decoder 3, control block 4, first 5 and second 6 counters, switch 7, first 8 and second 9 registers, group of moment calculation blocks 10, and control block 4 contains a generator 11 clock pulses, trigger 12, element I13, register 14. element 15 of combinational logic, first memory block 16 (positions 11-16 are not shown in the drawing).

The moment calculation unit contains the second memory block 17, the first group of accumulating adders 18. A group of switches 19, accumulating the adder 20.

The device works as follows.

Before starting, an image of the object is projected onto the matrix 1 of photoconverters, which contain x cells, each of which converts an optical signal into a proportional electrical signal.

Upon the arrival of the signal on the start bus of control unit 4, register 14 is zeroed, trigger 12 permits the passage of pulses from generator 11 to register input 14. The first memory block 16 is sampled at address 0000. At the outputs of the control block and the output of the first memory block 16 single potentials appear, the microoperation of the first block of the algorithm, i.e. the accumulating adders 18 and 20, counters 5 and 6, registers 8 and 9 are zeroed. Thus, the device was prepared for the initial state.

With the arrival of the signal at the third control input of the second register 9, a code is set at its output that determines the mode of operation of the device. If the zero register of the register is one, then the mode of calculating the moment characteristics of the image is performed.

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If zero, then the end of work mode.

A sample of cells of the photovoltage matrix 1 starts from the 0th column and from the 0th row at the address generated by the first counter 5, from the output of which the values of the least significant bits are fed to the input of the decoder 3, which forms the column number; the values of the higher bits from the output of the first 5 counters are fed to the input of the switch of 7 lines, which selects rows.

The analog signal read from the matrix cell 1 of the photovoltaic cells is converted by analog-digital converter 2 into a digital code that is stored in the first register 8.

At the address produced by the first counter 5 simultaneously with the sampling of the cell of the array 1 of photodetectors, the sample of the Permanent Memory device also occurs. The second memory block 17 is read, depending on which the accumulated total intensity of the image fragments is accumulated in the first accumulating adders for each bit of the binary decomposition.

Similarly, the sampling and processing of the contents of the 4 following cells of the matrix 1 of photovoltaic cells occurs.

After sampling (t, n) - the cells in the first accumulating adders 18 will find the total intensities of the image fragments for each bit of the binary decomposition.

The further process of calculating the moment characteristics is reduced to the weight accumulation of the total intensities of the image fragments, this operation can be carried out in the form of summation of accumulated adders 18 shifted by the appropriate number of bits of bits. For this purpose, the switches 19, formulated in the first accumulating adders 18, go to the inputs of the zero switch 19, the values of the first bits to the input of the first switch 19 hours, and so on. the values (n-1} of the bits of the first accumulating adders are fed to the input of (p-1) -th switch 18.

The control inputs of the switches 19 simultaneously receive the code generated by the second counter 6 operating in the direct counting mode, thus the output of the switches 18 successively appear the values of the total fragment intensities for zero, first and

Claims (1)

1. An apparatus for detecting image features comprising an array of photoconverters, an analog-to-digital converter, a first decoder, a control unit characterized in 0 that, in order to increase the speed of the device, to expand its scope of application due to the possibility of calculating moments of higher orders, two counters, a switch, two registers and 5 group of moment calculation blocks, second and tenth outputs of control unit are connected to information input and control input of first counter, the first output of which is connected to input of de encoder and second information inputs of moment calculation blocks, and second output of first counter is connected to control input of switch and with the first informational inputs of the blocks 5 calculation of the moments, the information input of the switch is connected to the output of the matrix of photovoltaic cells, the input of which is connected to the output of the decoder, the output of the switch is connected to the information 0 an analog-to-digital converter input, the control input of which is connected to the sixth output of the control unit, and an output of the analog-digital converter connected to the information input of the first register, the first and second control inputs of which are connected to the seventh and third outputs of the control unit, the fourth and the third outputs of which are connected to the first and second control 0 inputs of the second register, the information input of which is the input for selecting the operating mode of the device, and the output is connected to the fourth information input of the control unit, the output of the first register 5 is connected to the third information inputs of the moment calculation unit, the fourth information inputs of which are connected to the first output of the second counter, the first and second control inputs of which are connected to the second and twelfth outputs of the control unit, the third output of the first and second output of the second counter are connected to the third and the second information inputs of the control unit, the eleventh, the ninth, the first, the eighth and The fifth fifth outputs of which are connected to the first, second, third, fourth, and fifth control inputs of the moment calculation units, the outputs of which are the outputs of the device. 2, The device according to claim 1, wherein the moment calculating unit contains a memory block, a first group of accumulating adders, a group of switches, an accumulating adder, the first and second inputs of the address of the memory block are the first and second information inputs of the block, the first and second control inputs are the fourth and fifth control inputs of the block, the outputs of the memory block are connected to the first control inputs of the accumulating adders of the group, the second and third control inputs of which are the second and 0 the third control inputs of the block, and the information inputs of the accumulating group adders are the third formation input of the block, the information input of the group switches is the fourth information input of the block, the control inputs of the switches are connected to the outputs of the group accumulating adders, the outputs of the switches are connected to the information input of the accumulator , the first and second control inputs of which are connected to the first and third control inputs of the block, the output of the second accumulating adder l is the output unit. I 4-Ь -with about-: