SU1580555A1 - Digit-analog servo converter - Google Patents

Abstract

The invention relates to analog-to-digital converters and can be used in the field of computing and measuring equipment, as well as in automated process control systems and in research automation systems. The purpose of the invention is to increase reliability while simultaneously expanding the input signal range. To do this, the first, second, and third logic blocks, the first and second triggers, the comparison block, the digital-to-analog converter, the reversible counter, the two AND elements, the delay element, the AND element group, the pulse distributor, zero-body are inserted into the converter containing the clock pulse generator. , a group of elements EXCLUSIVE OR, two inverters and a trigger. At the same time, the presence in the device of the group of EXCLUSIVE OR elements of the first inverter and the zero-organ allows the bipolar input analog signal to be processed, and the introduction of the trigger and the second inverter allows increasing the reliability of the converter. 1 hp f-ly, 2 ill.

Description

The invention relates to analog-to-digital converters and can be used in computing and measurement technology, as well as in automated process control systems and automation systems for scientific research.

The purpose of the invention is to increase the reliability and expansion of the field of application by increasing the input signal range.

Figure 1 shows the functional diagram of the following analog-to-digital converter; figure 2 is a functional diagram of the third logical block.

The converter contains a comparison unit 1, a digital-to-analog converter 2 (D / A converter), a zero-body 3, an element NOT 4, a group of elements EXCLUSIVE OR 5, logical blocks 6-8, a reversible counter 9 consisting of triggers 10, first P, second 12 and the third 13 triggers, groups of elements AND 4, distributor 15 pulses, generator 16 clock pulses, element 17 of delay, element NOT 18, elements AND 19 and 20. The third logic unit contains the element EXCLUSIVE

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00

o ate sd ate

OR 21, element NOT 22, elements AND 23 and 24.

Comparison unit 1 serves to compare the input signal U with the reference level U0. The signal S at its output is equal to O if U U0, and S 1 if Ux U0.

The null organ 3 is designed to compare the input signal U with a well: if U ,,. 0, then the signal V at its output is equal to O, if their “GO, then V 1, the signal from the output of the zero-organ 3 has information about the sign of the input signal and goes to the output signal bus, and also through the first element HE 4 to the most significant bit of a digital-to-analog converter and the first inputs of a group of elements EXCLUSIVE OR. The signal from the outputs of the reversible counter passes to the lower bits of the digital-to-analog converter with inversion, if V 1, and without inversion, if V 0, thereby providing the four-quadrant operating mode of the digital-analog converter required to provide a two-polar reference level.

A trigger 11 serves to memorize the response of the comparator at the previous clock. The signal S at its output is equal to 1 m, if at the previous cycle the comparison unit outputs the signal S. The signal at the output of the first logic block 7 is equal to S Snvsn, where P is the signal from the output of the higher bit of the reversing estimator.

At the first output of the third logical block 8, the signal Ј1 appears at

changing the comparison block responses on two

four

consecutive clock cycles f (S0S, VS0S,) q, where S0 is the signal from the output of the first trigger I 1;

q - signal from the generator of 16 clock pulses.

At the second output of the third logic block 8, the signal appears when the responses of the comparison block of the last two cycles f (S0 S., VS0S,) q coincide.

The second logic unit 6 at S 1 sets the mode of subtraction of the reversible counter, and at the mode of addition.

The Converter operates as follows.

The initial setup signal sets the first 11, second 12, third 13 triggers and reversible counter 9 to

r

0

the zero state, and the code 0 ... 10 is set in the pulse distributor (the initial setting circuits are not shown. Since at the beginning and during further normal operation, the output of the higher bit of the reversible counter contains the signal P 0, the first logic block 7 passes to its output response of the comparator unit without inversion.

After the input signal is supplied, say, positive polarity (), the comparison unit 1 outputs the signal S, according to which with the help of the second logic unit 6 the reversible counter is transferred to the addition mode. Since the first trigger 11 stores the signal S, the third logic unit 8 generates a coincidence signal at the second output, which sets the second trigger to state 1. The signal from the delay element 17 adds one to the bit the reversible counter, determined by the pulse distributor, and rewrites the response of the comparison unit to the first trigger 11. After the third input of the third logic block 8 arrives the signal q from the 16 clock pulse generator, to its second output signal f2 0 appears, which, having passed through the second element NOT 18 and element 19, sets the third trigger 13 to state 1. Suppose that with the arrival of the next signal from the clock generator, the comparison unit I again produces a signal S, to which the second logic block 6 confirms the addition mode on a reversible counter, and the third logic block 8 generates a match signal, which, having passed through AND 20, shifts left by one bit the contents of the pulse distributor. After that, the clock signal delayed on the delay line adds a unit to the discharge of the reversible counter, determined by the distributor 15 pulses (the weight of this unit is twice the weight of the previous one), and rewrites the response of the comparison unit per trigger 11. If further the same answers from the unit of comparison (S), then everything happens in a similar way.

After the first shift of the block 1 comparison response, i.e. with the arrival of the signal S

The second logic unit 6 transfers the reversible counter to the subtraction mode, and the third logic unit 8 outputs at the first output a mismatch signal of the current (S) and previous (S) responses of the comparison unit, which shifts to the right by one bit of the content of the distributor J 5 pulses and sets the second 12 and third 13 triggers in O. Then, the signal from the generator 16 clock pulses, delayed by the delay element 17, subtracts one from the discharge of the reversible counter 9 defined by the pulse distributor, and the unit weight is two times for less than the weight of the previous one.

If the response of the compare unit 1 is changed again (S), then a shift to the right occurs, and the quantization step is halved. If the response of the comparison unit 1 is repeated (S), then due to the zero state of the third trigger 13, the shift in the distributor 15 pulses does not occur, the quantization step size does not change, but the trigger 12 goes to 1. Thus, the operation mode of the converter allowing to increase the reliability of the conversion. After that, with the arrival of the signal q from the 16 clock pulse generator, the signal f 0 appears at its output at the third input of the third logic unit 8, which, having passed through the HE element 18 and the AND 19 element, sets the third trigger 13 to the state 1. From the arrival of the next signal S due to the state 1 of the flip-flop 13 causes the contents of the distributor 15 to shift to the left and the quantization step is doubled

When changing the sign of the input signal (U 0), the output of the null organ 3 produces a signal V, which is fed to the first inputs of a group of EXCLUSIVE OR 15 elements, which passes to its outputs inverted signals from the outputs of the reversible counter 9, resulting in an exemplary level the output of the digital-to-analog converter changes its sign. Otherwise, the operation of the converter is similar to that indicated.

If, due to the high rate of change of the signal near the limits of the range, an overflow counter overflow occurs, i.e. set the code 01 ... 1 (lower and upper bounds

the same signal is determined by the maximum input signal module), then due to the position.} the higher bit of the reversible counter, the first logic block 7 transmits the inverted signal of the comparison block to its output. The operation of the other blocks of the converter coincides with the specified one.

The binary additional code characterizing the magnitude of the input signal is removed from the output of the EXCLUSIVE OR element group — the modulus of the number, and from the zero-organ output — the sign of the number.

Claims (1)

1. A next analog-to-digital converter containing a comparison unit whose first input is an input bus and the second input is connected to the output of a digital-to-analog converter, and the output is connected to the first 5 by the input of the first logic block, the second input of which is connected to the output of the higher bit of the reversible counter, and the output connected to the first input of the first trigger, to the input of the second about the logic unit and the first input of the third logic unit, the second input of which is connected to the output of the first trigger, and the third input is combined with the input of the delay element and connected to the output of the clock generator, the output of the delay element is connected to the second input of the first trigger and the first inputs of the group elements And, the second inputs of which are connected to the corresponding outputs of the pulse distributor, the first input of which is combined with the first input of the second trigger and is connected to the first output of the third logic block ka, the second output of which is connected to the first input of the first element I, the output of which is connected to the second input of the pulse distributor, the first input of the second element I is connected to the output of the second trigger, the outputs of the second logic unit are connected to the control inputs of the reversible counter, the installation inputs of which are connected to the corresponding outputs of a group of elements And, differing in the fact that, in order to increase the reliability and expand the scope of application by increasing the input signal range, a third trigger has been introduced, per5 0 five 0 five B about 1 FIG. 2