SU915095A1 - Analyzing filter of digital vocoder - Google Patents

Description

The invention relates to speech analyzers' based on a linear prediction algorithm and can be used in a vocoder analyzer.

Known speech analysis devices based on a linear prediction algorithm in which. prediction coefficients are used

[one].

The disadvantages of such devices include the potential instability of the analyzing filter and the necessary large amount of the discharge grid of a specialized calculator.

A device for analyzing speech synthesis is known on the basis of partial correlation coefficients using the Itakak algorithm. The specified device is always stable, the coefficients

always less than one and when building a specialized calculator, a relatively small size of the discharge grid is required.

In the known device, the analyzing phyteter of a digital vocoder contains ten serially connected arithmetic

2

blocks. Each arithmetic unit contains a forward and backward residual calculator, a correlation computing device, and a division scheme.

A correlation computing device contains an adder or a subtractor, a shift register that performs a signal delay by a word length, a format converter, a serial-parallel register, a multiplier, a subtractor, an 'adder, shift registers.

The division circuit contains an adder, a subtractor, series-parallel registers, a parallel adder.

The residual “Forward” and “Back” calculators contain shift registers that delay the signal by word length, multipliers, the storage register of the calculated correlation coefficient, and subtractors [2].

A disadvantage of the known device is a large amount of equipment required for the implementation of the analysis algorithm.

The purpose of the invention is to simplify the device.

This goal is achieved by the fact that the analyzing filter of a digital vocoder.

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containing multipliers, the inputs of which are connected to the corresponding buffer registers, with the first inputs of the first and second multipliers combined and connected to the first buffer register, adders, 5 divider and random access memory, the output of which through the second buffer register is connected to the second input of the first multiplier and through the fourth the buffer register to the first input of the third multiplier, the outputs of the second and third multipliers are connected to the corresponding inputs of the second adder, the outputs of the first o and the third adders are connected to the corresponding inputs of the divider, the output of which is, 5 output devices, multiplexers are entered, the first and second additional multipliers, the first and second additional operational memory and additional buffer registers, the first 20 inputs of the first and second multiplexers are combined and are the input of the device, the second input of the first multiplexer and the input of the first additional random access memory are connected to the output of the first 25 adder, the second input of the second multiplexer and the input of the second additional random access memory are connected to the output of the third adder, the output of the first additional operational memory is connected to the first input of the third multiplexer, the second input of which is connected to the output of the second adder, the output of the third multiplexer is connected via the corresponding additional buffer register to the first the input of the first additional multiplier, the second input of which is connected to the output of the fourth multiplex Ora, the output of the second additional random access memory is connected to the first input of the fifth multiplexer, the second input of which is connected to the output of the first multiplier, the output of the fifth multiplexer is connected via the corresponding additional buffer register to the first input of the second additional multiplier, the second input of which is connected to the output of the sixth multiplexer, output the first multiplexer is connected to the input of the first buffer register and to the first input of the seventh multiplexer, the second input of which combined with the second input of the eighth multiplexer and connected to the output of the divider, the first input of the eighth multiplexer is connected to the output of the random access memory, the output of the seventh multiplexer is connected to the input of the third buffer register, the output of the eighth multiplexer is connected to the input of the fifth buffer register, the output of the first additional multiplier

four

connected to the first inputs of the ninth and tenth multiplexers, the output of the second additional multiplier is connected to the first inputs of the eleventh and twelfth multiplexers, the second input of the ninth multiplexer is connected to the output of the first buffer register, the second input of the tenth multiplexer is connected to the output of the operational memory, the second input of the eleventh multiplexer is connected to the output of the third multiplier, the second input of the twelfth multiplexer is connected to the output of the second multiplier, the outputs of the virgins and eleventh order multiplexers are connected through respective buffer registers to the inputs of the first adder, the outputs of the tenth and twelfth multiplexers are connected through respective buffer registers to the inputs of the third adder.

FIG. 1 shows a block diagram of an analyzing filter; in fig. 2 - analysis graph; in fig. 3 - timing diagram of multiplexer operation; in fig. 4 - time diagram of the device.

The analyzing filter of a digital vocoder contains multiplexers 1-12, random access memory (RAM) 13-15, multipliers 16-20, adders 21-23, buffer registers 24-34, divider 35.

The first inputs of multiplexers 1 and 2 are combined and are the input of the device. The output of the adder 21 is connected to the first input of the divider 35, to the input of the RAM 14 and to the second input of the multiplexer 1, the output of which is connected to the first input of the multiplexer 7. and through the buffer register 24 to the first inputs of the multipliers 16 and 18 and to the second input of the multiplexer 9. Output adder 23 is connected to the second input of divider 35, to the input of the random access memory 15 and to the second input of the multiplexer 2, the output of which is connected to the input of the random access memory 13, the output of which is connected via the buffer register 25 to the second input ne of the multiplier 16, through the buffer register 28 to the first input of the multiplier 19 and directly to the first input of the multiplexer 8 and to the second input of the multiplexer 10. The output of the operational memory 14 is connected to the first input of the multiplexer 3, the second input of which is connected to the output of the adder 22. The multiplexer output 3 through the buffer register 26 is connected to the first input of the multiplier 17, the second input of which is connected to the output of the multiplexer 4. The output of the multiplier 17 is connected to the first inputs of the multiplexers 9 and 10. The output of the operational backup the repeating device 15 is connected to the first input of the multi 915095

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type 5, the second input of which is connected to the output of the multiplier 16. The output of multiplexer 5 is connected via the buffer register 30 to the first input of the multiplier 20, the second input of which is connected to the output 5 of the multiplexer 6. The output of the multiplier 20 is connected to the first inputs of the multiplexers 11 and 12. The output of the divider 35 is connected to the second inputs of multiplexers 7 and 8.

The output of the multiplexer 7 through the buffer register 10 is connected to the second input of the multiplier 18. The output of the multiplexer 8 is connected via the buffer register 29 to the second input of the multiplier 19. The output of the multiplier 18 is connected to the first input of the multiplexer 12. The multiplier output 19 is connected to the second input of the adder 22 and to the second input of the multiplexer 11. The outputs of the multiplexers 9 and 11 through the corresponding buffer registers 31 and 20 32 are connected to the inputs of the adder 21. The outputs of the multiplexers 10 and 12 through the corresponding buffer s registers 33 and 34 are connected to inputs of the adder 23.

The output of divider 35 is the output of the device.

The device works as follows. The analyzing filter performs calculations in accordance with the analysis graph (Fig. 2). The object of the analysis filter ₃₀ is obtained chenie partial correlation coefficients

which are calculated by the formula

ί (η) = cG (p-1) -4 (1-c) -x ⁺ (l), x ^ .., (p),

d (n) = cd (n-1) +2 (1-с) {[x ^ _n . ₁ (p)] ² + (x ^ _., (P)] where the partial correlation coefficient;

c-constant averaging; x ^ c / n) —short “Forward”; 40

^X gp-C ^p ) -degree "Back";

t is the number of the filter cascade; η - the number of the current speech sample

signal;

M is the number of cascades. 45

The timing diagram of the operation of multiplexers is shown in FIG. 3. State "1" corresponds to the top position of the multiplexers in the block diagram.

To perform mathematical operations 50 in each stage of the filter, eight clock cycles are necessary (Fig. 4).

FIG. 4 marked:

П1 = х ^ (п) х ^. ₄ (p); P2 — s-1 (p-1);

PZ = [χίο. ^ Π)] ¹ ; П4 _β [χ ^,. ^ (Η)) ² ; 55

P5 = cd (p-1); C1 = PZ + P4; Pb = 2 (1-s) C1;

П7 = 4 (1-с) П1; C2 = P2-P7; NW = P5 + P6; d1 =; P8 = d1-x ^. _g (n);

A9 = ₉ 1 · χ ', “. <(Η); C4 = χζ ,. ₄ (η) -Π9;

C-5 = (η) - A8.

In the first clock, the signal from the output of the digital-to-analog converter 5 (p) is input to the analyzing filter and is written once per M cycles through multiplexer 1 to the buffer register 24. The value x ₀ "is extracted from the random access memory 13 and written to the buffer registers 25 and 28, as well as through the multiplexer 8 into the buffer register 29. From the random access memory 14, the value ΐ (η-1) is retrieved and written through the multiplexer 3 to the buffer register 26. The value is retrieved from the random access memory 15 on d (n-1) and is written through multiplexer 5 into the buffer register 30.

In the second cycle, all five multipliers work in parallel. The multiplier 16 calculates the product P1, the multiplier 17 - P2, the multiplier 18 - PZ, the multiplier 19 P4, the multiplier 20 - P5. In the same cycle, the input signal is recorded in the random access memory 13.

In the third cycle, the adder 22 calculates the sum C1, and at one input it comes from the output of the multiplier 18 the value of the PZ, and to the other input from the output of the multiplier 19 - the value of P4.

At the beginning of the third cycle, the multiplexers 2–8 are switched and the P5 product is output from the multiplier 20 output through multiplexer 12 to the buffer register 34.

In the fourth calculation cycle in the adder 22, the sum C1 via multiplexer 3 is written into the buffer register 26 and the multiplier 17 calculates the product P6, since the number 2 (1-С) comes from one multiplexer 4 to one input, and the second input to the second input register 26. In the same cycle, the product P1 through multiplexer 5 is written into the buffer register 30, and the multiplier 20 calculates the product P7, and at one of its inputs the number 4 (C-1) comes from multiplexer 6, and the second input is the product of P1 with buffer register 30.

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In the fifth cycle, the product P2 from the output of the multiplier 17 through multiplexer 9 is written to the buffer register 31, and the product from P7 from the output of the multiplier 20 through multiplexer 11 is written to the buffer register 32. The adder 21 calculates the difference C2. At the same time, the product 116 from the output of the multiplier 17 via the multiplexer 10 is written into the buffer register 33, and the adder 23 calculates the sum of the NW, since the number P6 enters one input from the buffer register 33 and the second input receives the number P5 recorded

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to buffer register 34 in the third cycle. The calculated value of C2 is recorded in the opera ’’

tive storage device 14, and the Sz in the random access memory 15.

In the sixth cycle on one input of the divider 35 5

served from the output of the adder 21 the number of C2 - dividend, and to another input from the output of the adder 23 the number of Sz - divisor. The divider 35 performs the operation d1. The output of the divisor 'is the calculated value of the partial correlation coefficient for the given cascade.

At the end of the sixth clock cycle, the multiplexers 9-12 are switched.

In the seventh cycle, the quotient of d1 from the output of divider 35 through multiplexers 7 15

and 8 is written to the buffer registers 27 and 29. The multiplier 18 performs the operation P8, with one input from the output of the buffer register 24, the number Χρ (η), and the other input from the buffer register 27, the number d1. ₂ o

In parallel with the multiplier 18, the multiplier 19 operates, which performs operation P9, with one input from the buffer register 28 being the number x (Cn), and to the other input the number d1. ₂ 5

In the eighth cycle, the product P9 from the output of the multiplier 19 through multiplexer 11 is written to the buffer register 32. A number is written to the buffer register 31 through multiplexer 9 from the output of buffer register 24. ed x £ (n). The adder 21 performs an operation C4.

In the same cycle from the output of the operational storage device 13 through the multiplexer 10, the number x ~ ₀ (n) is written into the buffer register 33, as well as from the output of the multiplier 18 ₃₅

through the multiplexer 12 is written in the buffer register 34 number P8. The adder 23 performs an operation C5. From the output of the adder 23, the information is recorded in the random access memory 13 via the multiplexer 2. At the same ₄₀ time, the information from the output of the adder 21 through the multiplexer 1 is written to the buffer register 24.

After the end of the eighth clock cycle, a new cycle of eight clock cycles arrives, and an arithmetic _<5 device performs all the operations for the second stage of the analyzing filter.

The proposed analyzing filter, in comparison with the known, reduces the amount of equipment.

Claims (1)

Claim A digital vocoder analysis filter containing multipliers whose inputs are connected to the corresponding buffer registers, with the first inputs of the first and second multipliers combined and connected to the first buffer register, adders, divider and random access memory, the output of which is connected to the second input of the first multiplier through the second buffer register and through the fourth buffer register to the first input of the third multiplier, the outputs of the second and third multiplier are connected to the corresponding inputs of the second adder, outputs of the first and the third adders are connected to the corresponding inputs of the divider, the output of which is the output of the device, characterized in that, in order to save equipment, multiplexers, first and second additional multipliers, first and second additional random access memory, and additional buffer registers, the first inputs of the first and second multiplexers are combined and are the device input, the second input of the first multiplexer and the input of the first additional random access memory are connected to the output the first adder, the second input of the second multiplexer and the input of the second additional random access memory connected to the output The third adder, the output of the first additional random access memory is connected to the first input of the third multiplexer, the second input of which is connected to the output of the second adder, the output of the third multiplexer is connected through the corresponding additional buffer register to the first input of the first additional multiplier, the second input of which is connected to the output of the fourth multiplexer, the output of the second additional random access memory is connected to the first input of the fifth multiplexer, W The main input is connected to the output of the first multiplier, the output of the fifth multiplexer is connected via the corresponding additional buffer register to the first input of the second additional multiplier, the second input of which is connected to the output of the sixth multiplexer, the output of the first multiplexer is connected to the input of the first buffer register and to the first input of the seventh multiplexer, the second input of which is connected to the second input of the eighth multiplexer and, connected to the output of the divider, the first input. "the eighth multiplexer is connected to the output of the operational storage device, the output of the seventh multiplexer is connected to the input of the third buffer register, the output of the eighth multiplexer is connected to the input of the fifth buffer register, the output of the first additional multiplier is connected to the first inputs of the ninth and tenth multiplexers, the output of the second additional multiplier under 9 915С The key is connected to the first inputs of the eleventh and twelfth multiplexers, the second input of the ninth multiplexer is connected to the output of the first buffer register, the second input of the tenth multiplexer is connected to the output of the operational memory, the second input of the eleventh multiplexer is connected to the output of the third multiplier, the second input of the twelfth multiplexer is connected to the output of the second transponder, the outputs of the ninth and eleventh multiplexers are connected via the corresponding additional buffer registers to the inputs of the first 5 10 the adder, the outputs of the tenth and twelfth multiplexers are connected through the corresponding additional buffer registers to the inputs of the third adder.