SU1027733A1 - Device for computing dynamic specturm - Google Patents

Abstract

A DEVICE FOR CALCULATING A SLIDING SPECTRUM, coAepwaujee first memory unit, arithmetic unit, synchronization unit, first and second address generation units, first output of the synchronization unit connected to the input of the first address generation unit, the output of which is connected to the first input of the first memory unit, second the input of which is connected to the second output of the synchronization block, the third output of the synchronization block is connected to the input of the second block of the formation of the address, so that, in order to expand the functional possibilities Due to the off / down view of the sliding spectrum with a Random displacement coefficient and a reduction in hardware costs, it contains a second memory block and three multiplexers, the fourth output of the synchronization block is connected to the control output of the first multiplexer, the output of which is connected to the third input of the first memory block, the output of which is connected to the first inputs of the second and third multiplexers, the control inputs of which are connected respectively to the fifth and sixth outputs of the synchronization unit whose seventh output is the connection With the first input of the second memory block, the second input of KdToporo is connected to the output of the second address generation unit, the output of the arithmetic unit is connected to the first input of the first multiplex (L ra and the second input of the second multiplexer, the third input of which is combined with the second input of the first multiplexer and is the input of the device, the input - 9 of the arithmetic unit is connected to the output of the third multiplexer, the output of the second multiplexer is connected to Q QO by the third input of the second memory block, the output of which is connected to the second input the third multiplexer and the third input of the first multiplexer, the EAE output of which is connected to the third 00 input of the first memory block, the first input of the synchronization block is the input of the device number code, the second input is the synchronization input of the device, the third input of the device indication and the fourth input - input setting the initial address of the device.

Description

11 The invention relates to computing technology and is intended to calculate cyclical, sliding and instantaneous spectra of signals using the fast Fourier transform algorithm. The invention can be used 3 spectrum analyzers operating in real time for digital signal processing in geology, medicine, and radar. Devices for detecting spectra of signals are known, including an arithmetic unit, a RAM unit, multiplexers, a control device 1. The disadvantage of analogs is the impossibility of calculating the sliding and instantaneous spectra of signals. The closest in technical essence to the present invention is a device for calculating cyclic and sliding spectra of signals using the fast Fourier transform (VPF) algorithm with a constant offset coefficient for the sliding spectrum Q / N, where N is the dimension of the array being processed, Q is the number input data, participating in the formation of the next array, and contains r 1/2 - 1 blocks of buffer memory, address formers, input device, control device, processor 2.. The spectrum of the signal is calculated on the basis of the fast Lurie transformation, and the processor includes a memory and arithmetic device. The disadvantage of the prototype is that the sliding spectrum in the device is calculated for only one value of the bias coefficient E. If necessary, the bias coefficient needs alteration. control device as well as change in the number and volume of buffer memory blocks, which makes the calculation of the sliding spectrum with an arbitrary hTOM C coefficient as well as (the instantaneous spectrum (i / N) practically impossible. The lack of a prototype can also be attributed to the presence of buffer memory blocks, which increases the hardware costs of the device, especially for small C. The purpose of the invention is to expand the functional capabilities of the device by turning off the sliding, with an arbitrary bias factor, and instantaneous spectra, as well as reducing the amount of -5 hardware costs. 3 The goal is achieved by the fact that a device for calculating slides of a single spectrum containing the first memory block, an arithmetic unit, a synchronous block first and second address formation units, the first output of the synchronization unit is connected to the input of the first address generation unit, the output of which is connected to the first input of the first memory block, the second input of which is connected to the second output of the synchronization unit, the third output of the synchronization unit is connected to the second block of the address generation, additionally contains the second memory block and three multiplexers; the fourth output of the synchronization block is connected to the control input of the first multiplexer, the output of which is connected to the third input of the first memory block, the output of which is connected to the first inputs of the second and third multiplexers, the control inputs of which are connected respectively to the fifth and sixth inputs of the synchronization unit, the seventh output of which is connected to the first input of the second memory block, the second input of which is connected to the output of the second address generation unit, the output of the arithmetic 6 unit is connected to the first input of the multiplexer and the second display of the second multiplexer, the third input of which is combined with the second input of the first cartoon The multiplexer is the input of the device, the input of the arithmetic unit is connected to the output of the third multiplexer, the output of the second multiplexer is connected to the third input of the second memory block, the output of which is connected to the second input of the third multiplexer and the third input of the first multiplexer, the output of which is connected to the third input the first memory block, the first input of the synchronization block is the input of setting the code of the device number, the second input is the synchronizing input of the device, the third input is the input of the setting of the device characteristic, and the fourth entry is the setup input of the device’s starting address. FIG. 1 shows a device, a functional diagram; in fig. 2 block diagram of the algorithm; in fig. 3 block diagram of the synchronization unit. The circuit of FIG. T) includes input 1 of the device, multiplexers 2 and 3, blocks i and 5 of the memory of the multiplexer 6, arithmetic unit 7, outputs 8-12 of the synchronization unit 13, blocks t and 15 of the formation of the address. ; -At the ENTRY 13 on the tires 16-19 push the code number accordingly. Q bus 16, sync pulses (SI ;, accompanying input data, sign of calculating cyclic or slits 1 and instantaneous spectra (bus 18, starting address (HA, bus 19) t equal to HA (N -1) - Q. The device calculates the spectral values M (N) of the original array of M Q (N) using the fast Fourier transform algorithm, whose graph is shown in Fig., In the applied algorithm, the laws of reading and writing operands on iteration are the same. Dl I denotes successive data arrays of a directed graph , through a (n) - the elements of the array M, where i Changes from O to P-1, P locjj, N, p 0,1,2, ..., N -1 COOT match the number of the node of the graph in the i-th array. 5 0,1,2 ,, .. indicates that the operands a j (n) and arrays / u (M) belong to the sth original array, or the formula for obtaining the elements of the array m | (N) from the elements of the ma 11-1 5/411, ... p Siva M (N) has the form I 1 (.. (g.) - c., (i -, f, о. ((2. (п) -о (. (n-Nf2 | - (1) Formula and JI is the basic operation. The algorithm of the HMF (Fig. 2) Formula (1) is implemented in the block 7 arithmetical block. The initial arrays M P (N) can be formed in two ways. The first method is blocked in the formation of the arrays fif (N) only from the data arriving at the device input, in this case 1 and as a result of the implementation of the fast Fourier transform algorithm, we have the cyclic spectrum of the arrays. The second method consists in the formation of arrays M (N) not only from the newly arriving data device input, but also from the previous data (.N of the original array. In this case, if 1 / N e 1, we have the sliding spectrum of the arrays, if 1 1 / N, then we have an instantaneous spectrum of arrays. Synchronization block 13 and blocks 1 and 15 (FIG. 3) are a specific example of a device with an arbitrary K, Block 13 contains 20 clock pulses with a loop cycle, the output of which is connected to the input of 21 clock counter pulses 21 and register clock 22, outputs 2,3, .., P bits counter 21 clock pulses are connected in a definite way to the inputs of multiplexers 23.1-ЯЗ.Р overflow output — to the input of counter 2C, iterations, the outputs of the counter of iterations are connected to the control inputs of multiplexers 23.1-23.P and the inputs of the gated decoder 25 of the first iteration output of the overflow counter of iterations one of the inputs of the element I 26, the other input of the element I 2b is connected to the inverse output of the trigger 27. The output of the element I 2b is connected to the counting input of the trigger 28, the direct output of the trigger 28 is connected to one of the inputs ale And 29, 30, 3 inverted output of the trigger 28 is connected to one of the inputs of the elements 32, 33, 31, as well as to the control input of the multiplexer 6 (Fig. 1), the outputs of the multiplexers 23.1-7-3. P are connected to the inputs of the register 22 and one of the inputs of the multiplexers 35 and 36, the outputs of the register 22 are connected to one of the inputs of the subtractor 37, to the other input of which the code G is fed from the inputs 16 of the operating mode control device, the outputs of the significant R bits of the subtractor arrive at the other input of multiplexers 35 and 36, and the output of the enacte discharge goes to another input of the elements And 29, 32, the control input of the relay is connected to the gate input of the decoder 25 of the first iteration, the output of the decoder 25 is connected to the third input element Both 23 and 32. The low bit of the counter 21 clock pulses is connected to the input of the inverter 38 and one of the inputs of the Element of the Orchid Or 39 and one of the inputs of the AND AO element, the output of the inverter 38 is connected to the input of the multiplexers 23.1-23.P, the output of the next bit Yes, the clock counter 21 is connected to one element input SPLAY10URUU1EEE OR 39, OTHER input element AND 0 and the input of the inverter k, OUTPUT element 39 is connected to the fourth input of elements AND 29 and 32, the output element ANDAO is connected to the third input of elements AND 30, 33 and to the input of the inverter A2, the output of the inverter and kl is connected to another input of elements AND 31 and FOR. The outputs of the elements 29 and 30 are connected to two control inputs of the multiplexer 35, two inputs of the element OR 43, and also to two control inputs of the multiplexer. FIG. 1, the outputs of the AND 32.. And 33 elements are connected to two control З inputs of the multiplexer ЗБ, two (the inputs of the element OR kk, and also two control inputs of the multiplexers 3 of Fig. 1), the output of the element 31 and 31 is connected to the third input of the element OR 43, the output of the element AND is connected to the third input of the element OR kk, the output of the element OR is connected to the control input of the memory block A (fig. D), and the output of the element OR to the control input of the memory block 5 (fig. 1 ), IN control mode control input 19 is connected to the installation inputs of the input data counter f5 and to the trigger input 27, the outputs of the counter 5 are connected to the inputs of the circuit AND-NOT 6 and the third input of the multiplexers 35 and 36. The process of calculating the spectrum according to the algorithm of the VPF in the device consists of loQ iterations. At the i -th iteration f .i ,, h S ,,, l, the array a is computed. Every .., 1 11 iteration consists of N / 2 steps. The elements a (n S,, j + 1) are calculated on ka m /; 1-m-, ° «a (n) and a (nf + N / 2 /). ° Each step in turn is divided into four clocks. On the first clock, the readout from the first memory block is performed on the operand af Щ S +), on the second step - read from the peranda a | n), h:, / oi - (- i S multiplication of the operand a {, n + N /. J by the weighting factor W and, in the case of 3 W к ,, оjjTM, performing the first iteration while calculating the sliding or instantaneous 5 / spectrv, writing the operand a (nf +) to the second memory block at address n +, On the third clock cycle Write to the first block of S // nl + l m ty operand a. (tvbN / 2i -), post from the arithmetic unit and under the above conditions, write to the second block of the operand ao (n) at the address (n - &). At the fourth step of each step, write the operand a (n - (- fS / 2 j into the first block iT-i of the memory and write to the second block of the memory of the operand a), coming from the input channel and related to the new array at the address (N-1-Q + t). If the cyclic calculation mode is set the array of arrays, the writing of the operands of the array M (N) to form the array M5 (M) in every second and third clock steps of the step is not performed, and in every fourth so j, Te of the step is allowed to record the input passed. After the completion of array formation (M) and the end of the calculation of the spectral components of the array M (N according to the Fast Fourier Transform algorithm, the memory blocks are swapped.) The memory block in which the array is formed (NJ participates in the calculation of the spectral components, and another memory block ti - in the formation of the array.) It should be noted that the necessary condition for the operation of the device is f-gi, where the frequency of the clock pulse of the generator is 10 clock pulses, f si is the frequency of the clock pulses accompanying the input information. Let us consider in detail the operation of the device by the example of calculating the slippery spectrum of the array M Q (N) at, and 2, 6 1/4. For the case of N 8 counts i-i i, the 21 clock pulses have hp1 - / r yes, the 2h iteration counter has 2 45 input addresses, bit, the number oe t "vo of multiplexers 23Л-23.Р is 3, the number of inputs of each of these multiplexers is 3, the register Reg.22 is 3, multiplexers 35 combine three-digit addresses direction in ONE. The blocks and 5 memories have a volume about the word “v,, o g the initial position of the counter 21. clock pulses, counter 2h itera o otion, trigger 2 for switching memory blocks are in zero state, register 22 can have an arbitrary state, trigger 2 / set: it is in zero state, at output SP D njTJi OWti. The ffi "gating decoder 25 is present in a single value, 111-010 101 is present at the control mode input ig. This code is written to the counter of the input data address at the g mode control input 16, the Q 010 code is set, at the input g there is a single potential which is a sign of the calculation of the sliding spectrum. At the control inputs of the multiplexers 23.1-23.3, there is code 00, which provides the formation of the write addresses and the readout of the data for performing the first iteration of the algorithm, at the outputs of the multiplexers: 23.1-23 3 3 we have the code 100. At the control; since the inputs of the elements 29 and 30 receive a zero potential from the direct output of the trigger 28 for switching memory blocks. Let code 00 at the control inputs of multiplexers 35 and ST allow the code to pass from the output of multiplexer 23.1-23.3 to the address input of memory blocks or memory block 5, respectively. At the address inputs of the k memory block, code 100 is present. At the inputs of the And 31 element, there are single values coming from the output of the inverter 1 and the inverse output of the trigger 28. The single value from the output of the And 31 element passes through the ISH "3, goes to control 4 input memory block. Let the single value at the control input, the memory blocks allow reading information from the memory blocks. We assume that the data of the MDLb array is written in the memory block C at the sequential addresses, then in the memory block 5 an array is formed. the output of the f {memory block is the operand of Q (4). The control of the input of multiplexer 6 contains the value 1. Let the unit value on the control of the input of multiplexer 6. permits the passage of information from the output of memory block 4 to the input of the arithmetic unit 7, and a zero value permits the passage of information From the output of memory block 5 to the input of the arithmetic block 7, At one of the inputs of elements 32 and 33, there is zero potential from the outputs of the elements E 39 and 0, respectively, then at the output of the elements AND 32 and 33, the code 00j is present; it also enters the control inputs of the multiplexer 36, allowing code 100 from the output of multiplexers 23.1-23.3 to pass to the address input of the memory block 5, at the outputs of the OR element 3 present t zero values of the element output unit, the potential is fed to the control input of the memory block 5, allowing reading data from the memory block 5. The data read from memory block 5 does not fall into the input of the arithmetic unit 7, since the control input of the multiplexer 6 contains a single value that permits the passage of information from the memory block k. Code 00 at the control inputs of multiplexer 3 permits the passage of data from the output of the arithmetic unit 7 to memory block 5. Therefore, the state of the control inputs of the multiplexers connected to the memory unit in which the next array is being formed is indifferent. Thus, in the initial state, the first cycle was executed, the first step of the device operation. In the second cycle of the first step, with the first clock pulse running, code 100 at the output of multiplexers 23.1-23.3 will be written into register 22, and the counter of clock pulses 21 will change to state 0001. The code at output of multiplexers 23.1-23.3 will change its value to 000. the control inputs of the multiplexers 35 and 36 and the control input of the block do not change from the memory block; The readout of operand a (0) at address 000. At the output of the memory block, there is an operand of (4) and in arithmetic block 7 multiplication of a is performed (4j by fj At the output of subtractor 37, the code 010 is formed in this clock cycle and its sign bit is a single value, which is a sign of the positive difference between the address of the operand LLP of the operand a (4) and the code 010 Q. This single value arriving at the input of the And 29 element will not change the state of its outputs, and entering the input of the And 32 will change the state of its output on the unit, since at the same time at the input element mA 32 There is a single value from the output of the EXCLUSIVE OR 39 element and inverter 2. The output state of the AND 33 element does not change. Thus, at the control inputs of the multiplexers 36 and 3 there is code 10, and at the control input of the memory block 5 Zero value. Code 10 allows code 010 passing from the output of subtractor 37 through multiplexer 36 to the address input of memory block 5 and Operand (M a h from memory output of memory block through multiplexer 3 to input of memory block 5, and a zero value on the control the input of memory block 5 allows recording opera as well as | (k) at address 010 in block 5 gtan ty. At this point, the second cycle of the first step ends. In the third cycle of the first step, with the arrival of the second clock pulse, the code

The 000 at the input of the multiplexers 23-123 .3 will be written into register 22, and the counter .1 clock pulses will change its state to OP10. The code for the output of multiplexers 23I-23.3 will change its value to TOP. The state of the control inputs of multiplexers 35, 2 and 6 does not change, and the control input of memory 4 is changed to zero due to the presence of unit values at the inputs of the AND 31 element. The zero value at the control input of memory k allows the writing of operands. At the output of the memory block in this clock cycle we have the operand a (0), and at the output of the arithmetic lock 7 the result is a (k) subtracting operand a5 (P) and operand a (4). Therefore, operand a (4) is written to memory block 4 at address 100.

At the output of the subtractor 37 in this cycle, the sign bit has a zero value, which is a sign of the negative difference between the address 000 of the operand a (P) and the code 010 S. This zero value, entering the input of the And 29 element, will not change the state of its outputs, and entering the input of the And 32 element will change the state of its output to zero. The output state of the AND 33 element does not change. Thus, at the control inputs of multiplexers 36 and 3 there is code 00 and the control input of memory block 5 is a single value that does not allow writing of operand a to the memory block 5, {0 ;. This completes the third cycle of operation of the device.

In the fourth cycle of the first step, with the arrival of the third clock pulse, the code 100 at the output of multiplexers 23.1-23о3 is entered into register 22, and the counter of clock pulses 21 changes to 0011. The code at the output of multiplexers 23.1-23.3 changes its value to 000. The multiplexers 35, 2 and 6 and the control memory unit k are unchanged. At the output of the arithmetic unit 7 in this cycle, we get the result of summing a (0) operand 8 (0) and a | (. Operand a (0) is written to memory block A at address 000. The fourth clock of each step is reserved for writing to memory block input data. If the input data (()) arrived at the device input before the fourth clock cycle, then the first clock pulse (SI) from the bus 17 will change

the state of the counter 5 is at 110, and the state of the trigger 27 by the first SI is changed to one. In this case, at the control inputs of the multiplexers 36

5 and 3 is present. Code 01, which is obtained at the expense of all units at the input of the And 33 element and a zero value at the input of the And 32 element. The sign bit code of the subtractor 37 does not affect the generation of control signals of the multiplexers 36 and 3 in the fourth clock cycle. . At the control input of the 5 memory block there is a value. Code 01. allows passage through

5 multiplexer 3B of the input address address given on the counter 5, and through multiplexer 3 of the given data itself to the input of the memory block 5. If the input is not received, then

0 idle read cycle from memory block 5.

At this point, the fourth cycle and the first step of the operation of the device ends. The next three steps of the device are similar to the first. After the fourth step has been completed, the clock counter 21 returns to the initial state 0000, and the transfer signal from its output changes the state of the counter 24 iterations to 01. This state,

acting on the control inputs of multiplexers 23.1-23.3, modifies the laws of the formation of the addresses of the write and read to perform the second iteration

algorithm (the sequence of formation of addresses is visible from the algorithm graph in Fig.), as well as entering the gated decoder 25 of the first iteration, changes the state of its output to zero, thereby prohibiting the formation of code 10 on And 32, 33 elements provides writing to the data memory block 5 from the output of the memory block 4.

 The third iteration of the algorithm is similar.

When the execution of the fast Fourier transform algorithm is completed, the signal from the overflow output 0 of the counter 24 iterations is fed to the input of the AND element 26.

If all input data participating in the formation of the array (8) is received at the input of the device, then 5, the counter 45 is in the state 111.: This state, arriving at the element, AND-NOT 46, changes the state of its output to zero which in turn

changes the state of trigger 27 to zero. A single value of the inverse output of the trigger 27 is fed to the input of the element And 2b, and a zero value from the direct output of the trigger 27 enters the input of the elements And 33 to prohibit the generation of a control code for recording the input data into the memory block 5. If the execution of the algorithm and the formation of the array M is completed (NJio, the signal from the output of the And 26 element changes the state of the trigger 28 for switching the memory blocks to the opposite, thereby connecting the memory block 5 to calculate the algorithm, and the memory block 5 to form the array ( N).

The operation of the device is repeated as described above.

If the cyclic spectrum of arrays is required to be calculated, then the state of input 18, controlling its modes of operation, is changed to zero to prohibit the generation of a single value at the output of the decoder 25, and hence the control codes for recording the data of array 1C (8). when forming an array (8). At input 19, when calculating the cyclic spectrum, code 111 is present.

It can be seen from the above example that by changing the state of the control inputs for each mode of operation, it is possible to calculate the sliding with an arbitrary t and instantaneous spectra of the signal.

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Claims (1)

DEVICE FOR CALCULATING A SLIDING SPECTRUM, containing the first Ch5 block of memory, arithmetic block, synchronization block, first and second blocks of address generation, the first output of the synchronization block is connected to the input of the first block of address generation, the output of which is connected to the first input of the first memory block, the second input which is connected to the second output of the synchronization unit, the third output of the synchronization unit is connected to the input of the second address generation unit, which, in order to expand the functional capabilities and by turning off the sliding spectrum with an arbitrary bias coefficient and reducing hardware costs, it contains a second memory block and three multiplexers, the fourth output of the synchronization block is connected to the control output of the first multiplexer, the output of which is connected to the third input of the first memory block, the output of which is connected to the first inputs second and third multiplexers, the control inputs of which are connected respectively to the fifth and sixth outputs of the synchronization unit, the seventh output of which is connected to the first m is the input of the second memory block, the second input of which is connected to the output of the second block of address formation, the output of the arithmetic block of connections to the first input of the first multiplexer and the second input of the second multiplexer, the third input of which is combined with the second input of the first multiplexer and is the input of the device, the input of the arithmetic block is connected with the output of the third multiplexer, the output of the second multiplexer is connected to the third input of the second memory block, the output of which is connected to the second input of the third multiplexer and The third input of the first multiplexer, the output of which is connected to the third input of the first memory block, the first input of the synchronization block is the input of setting the device number code, the second input is the synchronizing input of the device, the third input is the input of setting the device attribute, and the fourth input is the input of setting the device’s starting address. Yesh ^ha, 7t§ '^<bi