SU1161947A1 - Information input device - Google Patents

Abstract

1. DEVICE FOR INPUT OF INFORMATION, containing decoder, the first, second and third registers, the first memory block, the first trigger, the first element And, the first and second counters, the first and second delay elements, the output of the last connected to the first input of the first element And, the second the input of which is connected to the output of the first trigger, the input of which is connected to the output of the first memory block, the first one of which is connected to the input of the first delay element, the input of which is connected to the input of the second delay element, the output of the first trigger connection inen with the input of the second register and. is the control output of the device, the outputs of the second register group are information outputs. the devices, the inputs of the second register are informational inputs of the device group, characterized in that, in order to increase the speed of the device by organizing a bitwise com Fff-r- - - / i.-q I,; ... ..l .: -; - ::. g; - j t-. . "RataasSKj-: replicas of machine words of a given structure, multiplexers, the fourth and fifth registers, the second memory block, the control unit whose output is connected to the first input of the second counter and the input of the first delay element, the KQToporo output is connected to it the third input of the second delay element, the input of the control unit is connected to the second inputs of the first and second counters and is the third control input of the device, the outputs of the second counter are connected respectively. with the first control inputs of the multiplexers and the third input of the first memory block, the W inputs of the group of which are connected to the outputs of the first counter, the first input of which is the second control input of the device, the second input of the first memory block The first and second groups of the first memory block are connected respectively to the inputs of the fourth and fifth registers, the outputs of the last are connected to the inputs of the second group of the 4; i of the memory block whose outputs are connected to the input and the first group of the third register, the outputs of which are connected to the inputs of the first group of the second memory block and the inputs of the group of the second register whose input is connected to the input TpeTbei o of the register, the inputs of the second group of which are connected to the outputs of the corresponding multiplexers, the second inputs of which are connected respectively to the outputs of the decoder whose inputs are connected to the outputs of the fourth

Description

register, the outputs of the first register are connected respectively to the inputs of the group of multiplexers.

2. The device according to claim i, wherein the control unit comprises a third delay element, a generator, a second trigger, a second element And, a third counter, a decoder, the output of which is connected to the second input of the second trigger, the first input of which is connected to the output of the third element the delay, the input of which is connected to the second input of the third counter and is the input of the block; the output of the generator and the output of the second trigger are connected respectively to the first and second inputs of the second element I, the output of which is connected to the first inputs of the third counter and ka is the output block of the third counter outputs are connected to inputs of the decoder.

The invention relates to computing and can be used in various automated systems for processing experimental data for the preparation and input of information in a computer. A device for inputting information is known, comprising a control valve connected in series with a bit number counter, a bit comparison unit connected in series to a decoder and a write enable valve, and a bit number register, as well as a reset valve connected in series with a word count counter. , the unit for comparing words and the register of the number of words and J The disadvantage of this device is the limited scope of application due to the possibility of forming a masking word only from a fixed number of words. Properties of input information words containing a certain number of bits. The closest to the proposed technical essence is a device for entering information containing the first, second and third registers, sequentially connected delay element, first AND element and first trigger, OR element. , the first and second blocks of comparison, the second, third and fourth elements And, the first and second counters, the pulse generator, the output of which is connected to the input of the second element And, the decoder, the input of which is connected to the first the output of the first register and the first input of the first comparison unit. The output of which is connected to the second input of the first trigger and the first input of the first counter, the second input of which is connected to the output of the second element AND and the first input of the second register, the second input of the first register is connected to the first INPUT of the second comparison unit, the second input of which is connected to the output of the second counter, the first input of which is connected to the output of the second comparison unit, the second input of the first comparison unit is connected to the output of the first counter, the memory unit, the fifth, sixth and seventh elements And, the second trigger, p The third input of the third register is connected to the output of the sixth element I and the second input of the second counter, the first output of the third register is connected to its second input, the third input is connected to the output of the fifth element I, the first input of which is connected to the first inputs of the second meter and second trigger The output of which is connected to the first input of the sixth element And, the second input of which is connected to the output of the pulse generator, the first input of the RAM block is connected to the input of the delay element, the second input of the second register and is the first The control input of the device, the second input of the RAM block is the second Control input of the device, and the output of the RAM block is connected to the input of the second register, the third output of which is connected to the second

the input of the fifth element And, the fourth output is connected to the first inputs of the third and fourth elements And, the second inputs of which are connected to the inputs of the second trigger and the outputs of the OR element, the first input of which is connected to the output of the bit comparison unit, and the second input of the OR element is connected to the output the seventh element And, the first input of which is connected to the output of the delay element, and the second input of the seventh element And is connected to. the input of the decoder and the second input of the first element And the second input of the second register is the information input of the device, the first output is connected to the third input of the third element And, the second output is connected to the third input of the fourth element And, and the outputs of the third and fourth element And are connected with the fourth and fifth inputs of the third register, respectively, the output of the first trigger is connected to the second input of the second element, And the rise of the third register is the output of device 2,

The disadvantage of this device is the inability to form machine words containing measurement parameters, the constituent parts of which are located in one channel of the information frame.

In addition, this device allows you to form machine words containing measurement parameters only if their constituent parts are received sequentially, i.e. There is no alternation of incoming components in the input data stream belonging to different parameters. If such an alternation exists, it is necessary after the layout of the corresponding parameters. Record a new editing program in the main storage unit and rerun the input data set in order to compile other measurement parameters, which leads to a sharp decrease in the device performance. At the same time, there is no possibility of arranging the measurement parameters, the constituent parts of which do not have compact packaging in the frame channels, but the formation of parameters in this device is accomplished only by shifting, which limits the functionality of the device.

The purpose of the invention is to increase the fast. Role of the device by organizing a bitwise arrangement of machine words of a given structure -.

The goal is achieved by the fact that the first, second and third registers, the first memory block, the first trigger, the first element And, the first and second counter, the first and second delay elements, the output of the last are connected to the input device containing the decoder; the input of the first element I, the second input of which is connected to the output x of the first trigger, the input of which is connected to the output of the first memory block; the first input of which is connected to the input. the house of the first delay element, the output of which is connected to the input of the second delay element, the output of the first trigger is connected to the input of the second register and is the control output of the device, the outputs of the second register group are information outputs of the device, the inputs of the second register are information inputs of the device group , the multiplexers, the fourth and fifth registers, the second memory block, the control block, the output of which is connected to the first input of the second counter and the input of the first zade element, are added The terminal, whose output is connected to the third input of the second memory block, the second input of which is connected to the input of the second delay element, the input of the control unit is connected to the second inputs of the first and second counters and is the third control input of the device ,, / outputs of the second counter, respectively with the first control inputs of the multiplexers and the third input of the first memory block, the inputs of the group of which are connected to the outputs of the first counter, the first input of which is the second control input of the device, the second in od evil first memory is a first councils yuschim input device outputs ervoy first and second groups of memory connected bloa sootvetstvenn .chetvertogo inputs and fifth registers, the outputs of the latter are connected to inputs of the second group vtoroya memory node which outputs cos I

Dineny with the inputs of the first group of the third register, the outputs of which are connected to the inputs of the first group of the second memory block and the inputs of the group of the second register, the input of which is connected to the input of the third register, the inputs of the second group of which are connected to the outputs of the corresponding multiplexers, the second inputs of which are connected respectively to the outputs of the decoder, the inputs of which are connected to the outputs of the fourth-register, the outputs of the first register are connected respectively to the inputs of the group of multiplexers.

The control unit contains the third delay element, the generator, the second trigger, the second element And, the third counter, the decoder, the output of which is connected to the second input of the second trigger, the first input of which is connected to the output of the third delay element, whose input is connected to the second input of the third counter and is the input of the block, the generator output and the output of the second trigger are connected respectively to the first and second inputs of the second element AND, the output of which is connected to the first input of the third counter and. is the output of the block, the outputs of the third counter are connected to the inputs of the decoder

FIG. 1 shows a structural diagram of the proposed device for inputting information; FIG. 2 is a block diagram of the control unit.

The device (Fig. 1) contains the first register 1, multiplexers 2, the second register 3, the third register 4, the first counter 5, the second counter 6, the first memory block 7, the fourth

one

P1

2 13

P1

476

the register 8, the fifth register 9, the decoder 10, the second memory block 11, the trigger 12, the AND element 13, the first delay element 14, the second delay element 15, the control block 16, the information input 17, the first control input 18, the second control input input 19, third control input 20, information output 21,

control output 22.

The control unit 16 comprises a delay element 23, a trigger 24, a generator 25, an AND element 26, a counter 27, a decoder 28, an input 29, an output 30.

The device works as follows.

At the input 17 of the device, digital information is received in the form of a periodic sequence of information channels forming a certain frame, as well as service information Start of a frame (input 19) and signals accompanying information channels (input 20). The word width of the information channel is equal to m, so each channel can contain from 1 to tn measured parameters or their parts. At the same time, the arrangement of the parts of parameters in the channels and in the frame can be arbitrary. As an example, consider the operation of the device in preparation for entering into a computer, two parameters P1 and P2, located in 1, 2 and 13th channels of the information frame.

Table 1 shows the arrangement of the parts of the parameters P1 and P2 in the corresponding bits of the information channels; the numerator indicates the number of the parameter, in the denominator - the number of its discharge in the output word of the device

Table 1

P2

P1

P2

P1

P2

In the memory block 7, the data preparation program is entered in the form of a buffer address corresponding to each bit (parameter number) Block address structure

Channel number

At the same time, the channel number is jpa of the data preparation program, the bit bits of the block 7 address are asanna to the first block 7 for the channel metering parameter — its lowest value and P2 corresponding to

Tinker In tab. 2 shows the structure table. one.

1 2 3

four

m

one

2

3

m-1

m

control channel formation channel of the following structure:

Channel number yes

Table 2

P

P2 P1

2 1 bits Sign of the end of the formation of the parameter parameter 1 bit) 7 memory having the following form;

RAM Address

Address

Channel Number Bit Size Yes Channel Buffer

T In the initial state, the second memory block 11 is cleared, and in the first memory block 7 there is a data preparation program that can be recorded from the computer (input 18) or from the control panel. At the device input 17, a stream of experimental data of an arbitrary structure ( depending on the type of information Hctb4HHKa), as well as tracking sync pulses (input 20) and the Beginning of the frame feature (input 19), which zeroes the count 5. The tracking sync pulse of the 1st channel adds one to counter 5, zeroes counter 6 and starts block 16 upra events that produces a burst of m pulses, which follow with a certain frequency. The first impulse of the stack adds one to counter 6 and accesses block 7 at the address formed in counters 5 and 6. The contents of the first cell of Block 7 are read into registers 8, 9 and flip-flop 12. By the contents of register 9, which is by the parameter number P1, block 11 is accessed by the first burst of a burst delayed by a certain amount on the first delay element 14. The contents of the cell block 11 at address P1 (in this case, zero) is read into register 3. The code of the first discharge of the first channel stored in the counter 6 is allowed

RAM content

Sign of

The bit number of the parameter stakes the sampling of the first bits on all multiplexers 2 ,. and the contents of the register -B through the decoder 10 samples the corresponding multiplexer, in this case, the n-th (in Table 1). Thus, the first bit of the input register falls into the nth bit of register 3 and is stored there. The first burst of the stack, the second delay element 15 has passed, accesses block 11 at the same address P1 to memorize the contents of register 3. The second burst of the stack modifies the address to block 7 by adding one to counter 6 and reads the contents of the second cell 7 and the corresponding cell block 11. Since, according to the table. 1, the second bit of the first channel is not selected, the contents of register 8 must be zero, and therefore none of the multiplexers are selected. The third impulse of the stack adds one to counter 6, and then the device runs as specified. In this case, according to table. 1 register 9 contains the address code P 2, counter 6 - code 3, and register 8 code 2 and, consequently, the contents of the third bit of register 1 through the corresponding multiplexer are fed to the input of the second section i of register 3 and stored. After this, the contents of register 3 are sent to the memory at address 112. The fourth burst of the burst again modifies the address of the first channel. In this case, according to table. 1 in register 8 is code 1, in counter 6 is code 4, and in register 9 is code Ш, and the contents of block 11 at address Ш are entered in register 3, after which the contents of the 4th digit of register 1 are fed to memory in the first bit of register 3, the contents of which are then again stored in UE 11 at address P1. Similarly, the device works on the remaining channel sizes. With the onset of the second channel, its information is stored in register 1, and the accompanying channel, the sync pulse adds one to counter 5, zeroes counter 6, and restarts control 16. The operation of the device with the second channel is similar to that indicated. With the arrival of the thirteenth channel and rewriting of its first bit into the third bit of register 3, the formation of parameter P1 is completed, in the 1st, 3rd, 4th and hth bits of which the 4th bit of the first channel is placed, respectively The 1st bit of the 13th channel, the bit of the second channel and the first bit of the first channel. The end of parameter formation is determined by a special sign read from block 7. The contents of this bit are remembered on trigger 12. If the contents of trigger 12 are one, the formation of the parameter is completed and the corresponding pulse of the packet from the output of the second delay element 15 through element 13 rewrites the contents register 3 to register 4 and arrives at the control output 22 of the device as an impulse to accompany information to the pairs & t of P1 received at the information output 21 of the device. This impulse also clears the register 3, and the zero code value is written to block 11 at address P1. Thus, a matching cell is prepared to form this parameter in the next information frame. The device works in a similar way when forming the remaining parameters. The device allows any arbitrary rearrangement of the information frame in accordance with a predetermined program. The control unit 16 operates as follows. The sync pulse (si) of the channel tracking input 29 sets the counter 27 to the zero state, and the sync pulse delayed by the delay element 23 sets the trigger 24 to one and the frequency of the generator 25 begins to flow to the counting input of the counter 27 and to the control circuit output 30. When the contents of the counter 27 become equal to m j, the signal from the output of the decoder 28 resets the flip-flop 24 to O, and the flow of pulses to the output of the control circuit is stopped. Thus, for each SI, the control circuit carries a packet of b pulses. The device is connected to the channels (multiplex or selector) of the input-output computer and, unlike the device, produces the computer. rational, dense packing of machine words containing a set of predetermined parameters of a certain structure from input words of different structure and size for subsequent input into a computer, which -. It is possible to efficiently load the memory of a computer when processing experimental information and relieve the processor from unproductive data preprocessing operations.

52

h

yy

but

""

but

r

Oj

Cm

Th

Claims (2)

1. A DEVICE FOR INFORMATION INPUT, comprising a decoder, first, second and third registers, a first memory block, a first trigger, a first AND element, a first and second counters, a first and second delay elements, the output of the latter being connected to the first input of the first AND element, the second the input of which is connected to the output of the first trigger, the input of which is connected to the output of the first memory block, the first input of which is connected to the input of the first delay element, the output of which is connected to the input of the second delay element, the output of the first trigger is connected to the input the house of the second register and is the control output of the device, the outputs of the group of the second register are information outputs. devices, the inputs of the second register are the information inputs of the device group, characterized in that, in order to improve the performance of the device by organizing a bitwise layout of machine words of a given structure, multiplexers, fourth and fifth registers, the second memory block, control unit, output are introduced into it which is connected to the first input of the second counter and the input of the first delay element, the output of which is connected to the third input of the second delay element, the input of the control unit is connected to the second inputs of the first of the second and second counters and is the third control input of the device, the outputs of the second counter are connected respectively. with the first control inputs of the multiplexers and the third input of the first memory block, the group inputs of which are connected to the outputs of the first counter, the first input of which is the second control input of the device, the second input of the first memory block is the first control input of the device, the outputs of the first and second, groups of the first memory block connected respectively to the inputs of the fourth and fifth registers, the outputs of the latter are connected to the inputs of the second group of the second memory block, the outputs of which are connected to the inputs of the first group the third register, the outputs of which are connected to the inputs of the first group of the second memory block and the inputs of the group of the second register, the input of which is connected to the input of the third register, the inputs of the second group of which are connected to the outputs of the corresponding multiplexers, the second inputs of which are connected respectively to the outputs of the decoder, the inputs of which are connected to the outputs the fourth SU „1161947 registers, the outputs of the first register are connected respectively to the inputs of the group of multiplexers. 2. The device according to claim 1, characterized in that the control unit; contains a third delay element, a generator, a second trigger, a second AND element, a third counter, a decoder whose output is connected to the second input of the second trigger, the first input of which is connected to the output of the third delay element, the input of which is connected to the second input of the third counter and is the input of the block, the output of the generator and the output of the second trigger are connected respectively with the first and second inputs of the second element And, the output of which is connected to the first inputs of the third counter and is the output of the block, the outputs of the third counter with unified with decoder inputs.