SU1432516A1 - Apparatus for dividing frequencies of two pulse trains - Google Patents

Abstract

The invention relates to computing and measurement technology and can be used for the functional processing of pulse frequency signals. The purpose of the invention is to improve the accuracy of dividing and expanding the field of application due to the possibility of dividing both the higher frequency into the smaller and the smaller into the greater. The device contains the first 1, second 2 and third 3 counters, the first 4 and second 5 registers and the delay element 6. The expansion of the field of application is achieved by introducing into the device a third counter 3, a second register 5 and a delay element 6. 1 il. from €

Description

The invention relates to computing and can be used to functionally process pulse frequency signals. , The purpose of the invention is to improve the accuracy of dividing and expanding the field of application due to the possibility of dividing both a higher frequency into a smaller one and a smaller one by a greater one. | Q

The drawing shows a functional oval diagram of the device.

A device for dividing the frequencies of two pulse sequences contains the first 1, second 2 and third and 3 counters, the first 4 and second 5 registers and the delay element 6 with corresponding connections.

The device divides the frequency f by frequency f. 20

Consider the case when f, f.

In this case, the meter 1 is filled faster than the counter 2. An overflow pulse from the output of the meter 1 arrives at the counter input of the counter 25 3. The latter is also organized as a chain of counting steps, each of which counts the number of pulses equal to B - 1. Counter 3 counts the number of pulses, the overflow pack coming from the output of counter 1, until counter 2 overflows. By this time, the number of pulses received at the input of counter 1 is t-B + C, where. m is the number of overflows of counter 1, n is its size, C is the remainder, B is the base of the number system.

The values of m and C are recorded in counters 3 and 1, respectively.

The number of pulses received at the input of counter 2 to the same point in time is equal to B.

It's obvious that

35

40

45

TV B

 m 4-g-R,

where m and -f; - correspondingly, whole 50 and fractional parts of the result of division.

Thus, in counters 3 and 1, the whole and fractional parts of the result of dividing frequency 4 by frequency f are recorded respectively.

The overflow pulse from the output of counter 2 enters the inputs once

0

5 n

five

0

five

0

five

solving register 4 and 5 and rewrites the values from counters 1 and 3, respectively. At the same time, this overflow pulse through delay element 6 goes to the reset inputs of counters 1 and 3 and sets them to zero values. Registers 4 and 5 remain recorded, respectively, from the start of the fractional and integer parts of the result of dividing the frequency f by the frequency f.

Consider the case when f, f.

In this case, counter 2 is filled faster than counter 1. By the time counter 2 is full, some value C is recorded in counter 1, and C from B. Obviously,

f, С „

t-; In view of the above, we-g.

The character C is a fractional part of the result of the division. The whole part is zero in this case. The overflow pulse, which appeared at the output of counter 2, writes to the register 4 the fractional part of the division result. In register 5, a zero value is written, because the counting input of counter 3 does not receive a single pulse.

In the particular case when the decimal number system is used, i.e. At 10, counters 1, 2, and 3 are binary digits.

Thus, the proposed device has an advantage in comparison with the known one by expanding the field of application by providing the possibility of dividing both the smaller part by the larger part and the greater by the smaller one and increasing the accuracy by making it possible to specify any necessary number of bits in the fractional part of the division result. .

Claims (1)

Invention Formula A device for dividing the frequencies of two pulse sequences, containing the first and second counters and the first register, the counting inputs of the first and second counters being information inputs of the device, characterized in that, in order to improve the division accuracy and to expand the scope due to the possibility of dividing as more frequencies to lower so 31432516 and a smaller one to a larger one, the second one is connected to it respectively the third counter, the second register and the information inputs of the second re delay element, and the discharge register, the output of the overflow pulse the outputs of the first counter connected to the second counter are connected to the input, respectively, with the information resolution of the first record and the input of the first register, the output of the first register and the input of the element the overflow pulse of the first counter-delay, the output of which is connected to ka connected to the counting input of the three-input reset inputs the counter, the bit outputs of the counters JQ.