RU1789990C - Device for quick walsh transform on sliding interval - Google Patents

Abstract

The invention relates to automation and computer engineering and can be used for processing digital signals, even and non-even 1xH6, 6, in image processing systems, for digital filtering, data compression, for spectral and correlation analysis of random processes, in communication systems, etc. .d. The aim of the invention is wider.

Description

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improving its functionality by calculating the Walsh transform coefficients, ordered by repetition rate. The goal is achieved in that the device contains computing modules l-ln. registers

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  ; mZTG AND ":: -.-; The invention relates to the field of automation and computer engineering and can be used for processing digital signals, even and odd sequences, in image processing systems, for digital filtering, data compression, for spectral and correlation analysis random pro, in communication systems, etc .;

The purpose of the invention is to expand the functionality of the possibilities by calculating the coefficients of the Urls transform with ordering in repetition rates.

In order to process even and odd sequences and to extract even and odd signals, it is proposed to use the odd-even odd Wallet transform based on the coefficients of which the even and odd sequences are determined. The even-odd Walsh transform matrix W2 ™ in the upper half represents the even Cal (k, j) Walsh functions, and in the lower half, the odd Sal (kJ) functions arranged in order to increase the repetition rates.

The matrix L / 2P dl has the form:

1111111 1 1 ---- 1 1 1--1 1--1 w (cs) 1-1-1-1-1 81111 ---- 1 1-1 1-1-1-1-1 1- 1 -1 -1 -1 This goal is achieved by the fact that the device contains a switch and an EXCLUSIVE OR element, the output of which is connected to the first information input of the switch, the output of which is connected to the second clock input of the fifth computing module, the second information input of the switch is connected to the first the input of the element ISKLYU2j (p), adders-subtracters 3j, switches, 5, the element EXCLUSIVE OR 6 and switch 7. The device implements a new algorithm for fast even-odd converts the development of Walsh. 7 ill.

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The singing OR and is connected to the nth clock input of the first group of the device, to the (n-1) g mutact input of the first group of which the second input of the EXCLUSIVE OR element is connected, the control input of the switch is the input of the device mode setting, and in the nth computing the control inputs of the first and second switches are connected to the second clock input of the computing module, the first and second outputs of which are the outputs of the first and second switches, respectively.

In FIG. 1 shows a graph of fast even-odd Walsh transform for N () S; FIG. 2 is a graph of fast even-odd Walsh transform on a moving interval for in FIG. 3 is a graph of fast Walsh transform with ordering in repetition frequencies for in FIG. 4 is a graph of fast Walsh transform with ordering in repetition frequencies in a moving interval for in FIG. 5 is a functional diagram of a device; in FIG. 6 is a circuit diagram of a switch, and in FIG. 7 is a timing diagram of the operation of the device.

The device (Fig. 5) contains n computing modules 1g-1p, registers 2j. ri), adders-subtracters 3j, switches 4j, 5, the element EXCLUSIVE OR 6 and switch 7, information input 8, mode 9 input, information outputs 10.11.

The switch (Fig. B) contains two elements And 12,13 and the element is NOT 14.

Register 2i in the first computing module performs a delay of one clock cycle, and the register in each subsequent computing module performs a delay of four times as much as in the previous module. In the 1st computing module, register 2i is 4-bit.

The clock frequency of register 2 is equal to the sample rate of the input signal, and for each subsequent register is doubled. This allows you to get the conversion factors in

real time and on a moving interval.

Sequences of length N, defined on a moving interval, consist of the current values of the samples of the input signal from the 0th to the (S-1} -th, from the 1st to the Nth, from the 2nd to (M + 1) -and readings, etc.

The selection of the operating mode of the device is carried out by a signal that is supplied to the input 9 to control the operating mode. When a signal is input to the input 9 of the switch 7, which is equal to logical 1, the device operates in the Walsh transform mode with ordering according to the repetition frequencies, and when a logical O signal is applied, in the mode of even-odd Walsh transform. All computing modules, except the nth module, work regardless of the operating mode of the device.

The device operates as follows. .. ... ...

The input sequence {x (1) -x (N)}, which represents the current values of the samples of the discrete signal, with a frequency fT (Fig. 7) of clock pulses is fed to the second input of the adder-subtractor 3b, which is activated in each cycle, and to the information the input of register 2i in the first computing module, where it is delayed by one clock cycle (one signal sample is stored in the register). The sum of the switch is output to the output of the switch 4h during each clock cycle, and then the difference generated at the outputs of the adder-subtractor 3i, is started from the second clock cycle (the sum and difference of the first two samples from the previous input sequence are generated and output in the first clock cycle). Register 2i and switch 4i are controlled by clock signal 1 (Fig. 7} from the first clock input of the first computing module.

Data from the output of switch 4i is supplied with a clock frequency of 2 fT to the second input of adder-subtractor B and to the information input of register 22, which is controlled by clock signal 2 (Fig. 7) from the first clock input of the second computing module. In register 1d, data is delayed by four clock cycles. During each clock cycle of register 2 in odd clocks, the output of the switch 4a, which is controlled by the clock signal 3 (Fig. 7) s, of the second clock input of the second computing module, displays the results: sum, then the difference, and in even clocks the difference, then the sum generated at the outputs of the adder-subtracter 32 in the second computing module:

(x (j) + xU + 4), x (j} -x (M),, 3, 5, ... xGMJ + 4) (xGMi + 4) ,, 4.6 ...,

starting with that beat. During the first four clock cycles, the results are generated and output: the sum and difference (difference and sum) of two pairs of samples consisting of the first five four samples from the previous input sequence.

In the k-th (, n-i) computing module, the data from the output of the (k-1) -ro computing module is fed to the second input of the sum of the subtractor 3k and to the information input of the register 2k with a clock frequency tV. In register 2k, which is controlled by a clock signal from the first clock input of the k-ro computing module, data is delayed by 5 clocks. The output of the 4k switch, controlled by the signal from the second clock input of the k-ro computing module, displays the results during each clock cycle of the 2k register in odd clocks: total, then the difference, and in even clocks. the difference is then the sum formed in accordance with the conversion graphs (Fig. 1 and 2) at the outputs of the adder-subtractor 3k in the k-th module:

5 . .. -.- ,. .. ..;., ...

fxffl + xG + f-1). xG) -xG + 4k-. 3.5, ... lxG) -xG + 4k 1), xG) + xG + 4k-1),. 4, 6, ...

starting with () -ro beat. During the first

0 4 clocks to the output of the 4k switch, the results obtained from the previous input sequence are output.

In the nth computing module, the data from the output of the (n-1) -th computing module 5 goes to the second input of the adder-calculator Зп and to the information input of register 2п with a clock frequency, where it is delayed by clock cycles. At the outputs of the adder-subtractor Зп in each clock cycle 2P,

0 controlled by the 6th clock signal (Fig. 7) from the first clock input of the computing module, the results are formed: the sum and the difference, which, depending on the operating mode of the device, are output to the outputs

5 of the first and second switches 4P and 5.

In the Walsh transform mode with ordering according to the repetition rates to the output 10 of the first 4P switch, which is controlled by the signal 6 from the first clock input of the computing module, with the frequency 2nfr, the sum and difference are displayed for each odd clock, and for every even tact - the difference and the amount formed in accordance with

5 by conversion graphs (FIGS. 3 and 4) to high-. the moves of the adder-subtracter Zp:

p-1

N

xOM-I 1) .3.5 ...., 7 | H

x, wG) P-1h

xG) -xG + 4n-1) /

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xG) -xG + 4n-1). J-2,4,6, ...-, y

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xG) + xG + 4n-1).

beginning of the e (4 + 1) th beat. During the first clock cycles, transform coefficients from the previous sequence are generated and output to the output of the switch 4P.

In this way; the current values of N Walsh transform coefficients with ordering by the number of steps from the first sequence (x (1) -x (M)} are obtained in the outputs of the subtractor-subtracter Зп in the ri-M computing module upon arrival of N- dtc4eTa i ouHoV6 signal and output to the output of the 4P switch with a frequency N times the clock frequency of the input signal samples. Upon arrival of the next (N + 1) -ro current sample of the input signal to the output of the 4P switch, new current values of the following N coefficients are output conversions from the second sequence {x (2) -x ( M + 1)} it.d;;

In the even-odd Walsh transformation mode, the switches 4P and 5 are controlled by the signal 7 (Fig. 7) from the second clock input of the computational xm6 barrel. At the same time in odd ticks on an exit. 10 of the first 4P switch with frequency fr, sums are derived, which are the coefficients xi ° (j) of conversion by even Cal Walsh functions with odd numbers from the first sequence {x (1) -x (M)}, and in even cycles differences, which are the coefficients xis (j) of the transform over the odd Sal functions

Claims (1)

SUMMARY OF THE INVENTION A device for performing fast Walsh transform on a moving interval containing p (2P - transform size) computing modules, the output of the 1st (, p-1) computing module being connected to the information input of a 1 + 1-gram computing module, information the computational module is the device information input, the first and second information BHxcflaWii are respectively the first and second outputs of the fifth computing module, the first clock input J-ro. p) the computing module is the J-M clock input of the first group of the device, the second clock input is m-ro (, r - the computing module is the rn-1 clock input of the second group of devices with even numbers formed at the outputs of the adder-subtracter 3Q: 5 10 15 20 N xic (lH GMJ + 4n-1), 1, 3, 5, ..., -y-1 in h i 2 N xicG) xG) -xG + 4n-1), J 2, 4, 6, ..., y At the same time, the outputs 11 of the second switch 5 output odd clocks, the differences representing the coefficients xis (j) of the conversion by odd functions with odd numbers, and into the even clocks, the sums, which are the coefficients of xisQ) of the conversion by odd functions with even numbers formed at the outputs of the adder subtractor Zn: xisG) xG) -xG + 4n; 1) ,, 3,5, ..., y-1 S / i n-h N xrG) xG) + x),, 4, 6,.,., y Thus, the current values of coefficients xi ° G) transformations by even Walsh functions are output to the output of the first 4P switch, and the current values for coefficients xisG), the transforms by odd functions are output to the output of the second switch 5 with a frequency of y fr before the (N + 1) -ro current signal of the input signal arrives. Upon the arrival of the next (N + 1) -ro sample of the input signal to the outputs of switches 4P and 5, new current values of the conversion coefficients from the following sequence {x (2) -x (N + 1)}, etc., are output. devices, and the Jth computing module contains a register, the adder-subtractor is a vt switch, and the nth computing module contains two switches / and in the jth computing module the output of the register is connected to the first input of the adder-subtractor. the outputs of the sum and difference of which are connected respectively to the first and second information inputs of the switch, and in the 5th computing module of the first and second switches, the second input of the adder-subtractor is connected to the information input of the register and is the information input of the computing module, the first clock input of which is the clock input of the register, and the mth computing module, the control input of the switch is connected to the second clock input of the computing module, and in the first computing module the first input of the switch is connected to the first clock input of the computing module, in the 1st computing module the output of the switch is the output of the computing module, characterized in that, in order to simplify the device and expand the functionality by calculating the Walshe transform coefficients with ordering according to repetition rates , it contains a switch and an EXCLUSIVE OR element, the output of which is connected to the first information input of the switch, the output of which is connected to the second clock input of the nth computed - - - 8b / reader Fig. I switch module, the second information input of the switch is connected to the first input of the EXCLUSIVE OR element and connected to the nth clock input of the first group of the device, to the p-1st clock input of the first group of which the second input of the EXCLUSIVE OR control input is the switch input is the task input device mode, and in the nth computing module, the control inputs of the first and second switches are connected to the second clock input of the computing module, the first and second inputs of which are the outputs, respectively first and second switches. / 2 EL. fl RFI Fie .6