SU1425707A1 - Device for performing fast walsh transform - Google Patents

Description

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The invention relates to automation and computing and can be used for digital spectral and correlation analysis of signals based on discrete orthogonal transformations in the basis of Walsh functions, for digital filtering, data compression, in communication technology, etc.

The aim of the invention is to simplify the device.

FIG. 1 is a functional diagram of the device; FIG. 2 is a time chart; in fig. 3 - fast Walsh-Pzli gras for dL, ().

The device contains registers 1, - 1 shift, adders-subtractors 2, - switches 3, -3, counters A and 5 ,. elements are NOT 6–9, elements 10–15, information 16 and clock 17 inputs and output 18. Register 1 shift, adder-subtractor 2; and switch: 3; form the i-th cascade transformed.

The device works as follows. .

The input sequence x ,, x,,, ..., representing the samples of a discrete signal, with a frequency of clock pulses, arrives at the input of the shift register I register 1 controlled from the output of the nth element HE 9, where it is delayed by one tick (in register 1, shift is stored one count). The operation of the adder-subtractor 2 controlled by the signal 2 (Fig. 2) from the first output of the first (low) bit of the counter 5 is synchronized in each even clock cycle. The output of the switch 35, which is controlled by the signal 3 (Fig. 2) from the output of the element AND 10 and operates at a frequency twice as large as the clock frequency of the shift register 1, during each clock cycle, starting with the second one, the sum is first output, and then the difference ,,

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In the (k 2-p) cascade 8 according to the transformation graph (Fig. 3), the sequence of intermediate data is delayed in register 1 by. cycles. The register of the K-th stage operates with a clock frequency of 2 times greater than the clock frequency of the register 11 of the shift of the first stage. Shift input register 1c shift

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The K-th stage is controlled by a signal from the output of the (2K-1) -th element I. The tiling of the subtractor of the 2k K-th stage is synchronized by a signal from the second output of the (K-1) -th element I, the Switch 3 of the K-th the cascade controlled from the code (2K-1) of the AND element works with a frequency twice as large as the clock frequency of the 1s shift register in the Kth cascade, and in the interval of each clock cycle it firstly displays the sum and then the difference formed in the K-th cascade.

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Thus, each subsequent conversion stage operates with a clock frequency of two times more than the clock frequency of the previous cascade. Therefore, at the output of the switch 3 of the last n-th stage, the transformations with a frequency 2 times the sampling frequency of the input signal, Walsh transform coefficients with Paley ordering are formed. In this case, the first X-factor of the transformation is obtained at the 2nd cycle after the arrival of the last 2 nd signal, and the last 2-nd factor Xjn, before the arrival of the () th sample. The pulse generator generates pulses with a frequency of 2.f, where f is the clock frequency of the samples of the input signal.

The proposed device in the sampling interval enumerates all the conversion factors from 2 samples of the input signal, which ensures its operation in real time.

Claims (1)

Invention Formula A device for performing a fast Walsh transform, comprising a first counter, the input of which is connected to a clock input of the device, n shift registers (2 is the number of transform coefficients), n subtractors, n switches, the information input of the first shift register and the summing input of the first adder the subtractor is connected to the information input of the device, the sum and difference outputs i-ro () of the adder-subtractor are connected to the information inputs of the 1st switch, the output j-ro (j 1-n-1) of the switch is connected to the information the j input (j + 1) -ro of the shift register and to the summing input (j + D-ro of the adder, output of the -th digit of the nth shift register is connected to the subtractive input of the nth adder-subtractor, output n- This switch is an output of the device, characterized in that, in order to simplify the device, it contains a second counter, n elements, NOT, 2n-1 elements II, and the input of the second counter is connected to the output of the nth digit of the first counter ( numbering from the side of the minor raer yes), the output of the i-ro discharge of the first counter is connected to the input of the i-ro element NOT, the output nj -ro element NOT and outputs up -15 20 425; 074. The rows from the first to the jth second counter are connected to the inputs (2j-1) -ro of the I element, the output of which is connected to the first input of the 2j-ro element I, to the control input of the j-ro switch and to the shift input (j + 1) -ro shift register, the second input of the 2j-ro element And is connected to the output (j + D-ro bit of the second counter, the output of the 2j-ro element And connected to the sync input j + 1) -ro of the adder-subtractor, clock the input of the device and the outputs of the bits from the first to the fifth of the second counter are connected to the inputs (2n-1) of the I element, the output of which is connected to the control input of the nth com utatora, yield -th discharge j-ro shift register is connected to a subtracting input of j-ro adder-subtractor. 4J BUT Jt0 eleven 70: Vocational school lp lpl giallll pshsh ZG CAOFKSHt / e - Fig.Z W) X {7) Threat