SU1552117A1 - Spectrum analyzer - Google Patents

Abstract

This invention relates to a digital electrical measuring technique. The purpose of the invention is to expand the frequency range and increase the resolution of the spectral analysis. The device contains an A / D converter A / D converter 2, registers 4, 30, synchronization unit 5, clock generator 7, divider 11, subtractor 13, memory unit 16, adder 17, discrete Fourier converter unit 18, comparison units 19, 20, counters 23, 24 and switch 27. A spectrum analyzer allows parallel spectral analysis with a small number of arithmetic operations and equipment, which expands the frequency range of the analyzed signals and increases the spectral solution. The high selectivity of synchronous accumulation increases the signal-to-noise ratio. 2 Il.

Description

JV JV

Yu

3

The invention relates to a digital electrical measuring technique and can be used for spectral analysis of signals against random noise.

The purpose of the invention is to expand the frequency range and increase the resolution of the spectral analysis.

Figure 1 shows the functional diagram of the spectrum analyzer; 2 a timing diagram of the operation of the synchronization unit.

The first input 1 of the spectrum analyzer (figure 1) is connected to an analog-to-digital converter (ADC) 2, the output 3 of which is connected to the input of the first register 4, the clock input of which is connected to the synchronizing inputs of the ADC 2, the synchronization unit 5 and the output 6 of the clock generator 7 pulses, input 8 of which is connected to an external master frequency generator and is the second input of the spectrum analyzer, the third and fourth inputs of which are inputs 9 and 10, which are connected respectively to the sample size and scaling factor codes, stroke 10 is connected to the second input of the divider 11, the first input 12 of which is connected to the output of the subtractor 13, the first input 14 of which is connected to the output of the register 4, and the second input is connected to the output 15 of memory 16, the second input of the Adder 17 and the first input of the discrete block Fourier transform () 18, the third input of which is connected to the input 9 of the spectrum analyzer, which is connected to the second inputs of the first 19 and second 20 comparison bdsks, the outputs 21 and 22 of which are connected to the inputs of the initial installation of the first 23 and second 24 counters, respectively to They are connected to the first inputs of the comparison units 19 and 20 and the first 25 and second 26 inputs of the switch 27, the output 28 of which is connected to the address input of the memory block 1 6, the input of which is connected to the output 29 of the second register 30, the input of which is connected to the output 31 an adder 17, the first input of which is connected to the output 32 of the divider 11, the clock inputs of the counter 23 and the register 30, the control inputs of the switch 27 and the memory block 16 are connected to the first output 33

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synchronization unit 5, the second output 34 of which is connected to the clock input of the counter 24 and the second input of the DFT unit 18, the first output 35 of which is connected to the second input of the synchronization unit 5, the second output 36 of the DFT unit 18 is the output of the spectrum analyzer.

Spectrum analyzer works as follows.

For each period of the master frequency f, which from the output of the external oscillator is connected to the input 8 of the generator 7 clock pulses (GTI), the generator 7 generates at output 6 a trigger pulse of the A / D converter 2, on the front of which the previously digitized signal x (l & t) is overwritten which enters input 1 of A / D converter 2, into register 4 (Figures 1 and 2} and initiates the next work cycle, AH. The same pulse triggers synchronization unit 5, which generates synchronization signals of devices of the spectrum analyzer at output 33 in accordance with the time diagram in figure 2. This will read the memory block 16 at an address that is determined by the state of the counter 23 and is transmitted from the input 25 of the switch 27 to the address input 28 of the memory block 16. The value read is subtracted by the subtractor 13 from the input reference and the result through the divisor 1I is transmitted to the input 32 of the adder 17, which summarizes the result of the division with the counting at the output of the memory block 16, the result is written to the register 30, and then to the memory block 16, after which the counter 23 increases its state by one. If the state of the counter 23 becomes equal to the value of the sample size code N, which is connected to the second input of the comparison unit 19, then its output 21 has a pulse that sets the counter 23 to the initial state. The DFT 18 block at any time can request data from the memory block 16 to enter the accumulated array. At the same time, it requests the memory access cycle of unit 16 via output 35, synchronization unit 5 switches switch 27 for transfer to output address 28 of memory unit 16, the output of counter 24, which determines the read address of the memory cell. Block 5 generates a read signal from memory block 16 according to your

a run 15 to a block 18, as well as a read write signal on output 34, on the falling edge of which counter 24 increases its state by one. If the state of the counter 24 becomes equal to the value of the N code, then using the comparison unit 20, it will be reset to the initial state. Code N is also connected to the third input of block 18, which with the help of this code controls the volume of the processed array. The code N, the code of the scaling factor M, which is connected to the second input 10 of the divider 1), and the reference frequency fs at the input 8 of the GTI 7 are the defining parameters of the spectrum analyzer. The spectrum analyzer allows you to perform a parallel spectral (harmonic) analysis with malm number of arithmetic operations and equipment, which allows you to expand the frequency range of the analyzed signals, to increase the spectral resolution. The high selectivity of synchronous accumulation increases the signal-to-noise ratio.

Claims (1)

Invention Formula A spectrum analyzer consisting of a clock generator, an adder, a first and a second counter, a memory unit and an analog-digital converter, the input of which is connected to the input of the spectrum analyzer, an analog-digital converter synchronization input connected to the output of the clock generator, the input of which is connected with the second input of the spectrum analyzer, which is different with the fact that, in order to expand the frequency range and increase the spectral resolution, the first register connected in series, the subtractor and a divider, and a second register, a switch, the first and second comparing units, one ten 15 20 5521176 a synchronization unit and a discrete Fourier transform unit, the first input of which is combined with the second outputs of the subtractor and adder and connected to the output of the memory unit, the first input of which is connected to the output of the second register, the first input of the last is connected to the output of the adder, the first input of which is connected to the divider output, the input of the first register is connected to the output of the analog-digital converter, the clock input of the first register is combined with the first input of the synchronization unit and connected to the output of the clock pulse generator The first output of the synchronization unit is connected to the control inputs of the memory unit, the switch and the clock inputs of the second register and the first counter, the output of which is connected to the first inputs of the first comparison unit and the switch, the second input of the switch is combined with the first input of the second comparison unit and connected with the output of the second counter, the clock input of which is combined with the second input of the discrete Fourier transform unit and connected to the second output of the synchronization unit, the first output of the discrete Fourier transform unit connected to the second input of the synchronization unit; the second output of the discrete Fourier transform unit is connected to the output of the spectrum analyzer. the third and fourth inputs of the spectrum analyzer are respectively the input of the scaling factor code and the input of the choice volume, the third is connected to the third input of the discrete Fourier transform unit and the second inputs of the first and second blocks of the comparison, the outputs of which are connected to ,, are the inputs of the initial installation of the first and second counters, the switch output is connected to the address input of the memory unit, the second input of the divider is connected to the input of the scaling factor code. 25 thirty 35