SU1264315A1 - Polyphase clocking generator - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in control systems, pulse distributors, computing devices. The purpose of the invention is the rubbing of the functionality achieved by forming nested sequences of pulses. To achieve this goal, a second register 5 and a D-trigger 6 are additionally introduced into the multi-phase generator. In addition, the generator contains counter 1, delay element 2, selector-multiplexer 3, first register 4, and input 7. The generator can be directly connected to control the number of devices equipment, for example, to storage devices on large integrated circuits. At the same time, the volume of equipment is reduced. 1 il.

Description

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The invention relates to a pulse technique and can be used in control devices, pulse distributors, computing devices, etc.

The purpose of the invention is to enhance the functionality of a multi-phase clock generator by generating nested sequences of pulses.

The drawing shows a circuit diagram of the device.

The multiphase MTG clock generator contains counter 1, delay element 2, selector-multiplexer 3, first 4 and second 5 registers and 1 flip-flop 6, D-input of which is input 7 of the device and connected to the input of setting zero of counter 1, output D-trigger 6 connected to the input of the zero-setting of the second register 5, and the synchronization input of the D-trigger 6 is connected to the control input of the selector-multiplexer 3, the data input of the first register 4 and the output of the counter 1, whose input is connected via the delay element 2 to the clock bus 8 and clock inputs the first 4 and second 5 registers, the first output of the first register 4 is connected to the first input of the first group of inputs and the last input of the second group of inputs of the selector-multiplexer 3 second output of the first register 4 is connected to the second input of the first group of inputs and the penultimate entrance of the second group of inputs of the selector-multiplexer 3, etc., the last output of the first register 4 is connected to the last input of the first group of inputs and the first input of the second group of inputs of the selector-multiplexer 3, the outputs of which are connected to the data inputs of the second register and 5, whose outputs are the outputs 9 MTG.

The device works as follows.

The input of the delay element 2, the clock input of the first shift register 4 and the clock input of the second register 5, which is the reference frequency input, receives the reference frequency pulses from the clock bus 8. After the delay element 2, the pulses arrive at the counter. Counter 1 and the first register 4 operate on the negative edge of the pulse, and the second register 5 - on

positive. Counter 1 divides the reference frequency by K times. Information from the output of counter 1 is fed to the C input of trigger 6, the serial data input of the first register 4, and the control input of the selector-multiplexer 3. Counter I has, as a rule, a significant delay in triggering compared with the first register 4, i.e. there is a delay from the arrival of a pulse at the input of the delay element 2 to a change in the signal at the output of counter 1, sufficient to reliably trigger the first 4.

The first register 4 records information present on the serial data input. This recording is performed on the falling edge of the reference frequency pulse from the clock bus 8. The information on the first output of the first register 4 changes with a delay of one clock frequency of the reference frequency relative to the serial data input, the information on the second lead of the first register 4 changes with a delay of two clock cycles, etc., the information at the Pm output of the first register 4 changes with a delay of P. There is a ratio of 3 p K between the coefficient K for dividing counter 1 and the number of outputs of the register.

Impulses from M-channel outputs

the selector-multiplexer 3 is received in two directions; one direction performs the switching of information from the outputs of the first register 4 to the inputs of the second register 5. At the same time, the first group; the inputs of the selector-multiplexer 3 receive information so that the first output of the first register 4 switches to the first output of the selector-multiplexer 3, the second output of the first the register is switched to the second output of the multiplexer-3, etc., the M-th output (Sfe M6p) of the first register 4 is switched to the M-th output of the selector-multiplexer 3; The second group of inputs of the selector-multiplexer 3 receives information from the first register 4 in the reverse order, i.e. The f-th output of the first register 4 is switched to the first output of the selector-multiplexer 3, (P -1), and the output of the first register 4 is switched to the second output of the selector-multiplexer 3, etc., (R-M + 1) -th output of the first

Claims (1)

Claim. A multiphase clock generator containing a pulse counter, a delay element, a selector-multiplexer, a clock bus, a register and an input bus, characterized in that, in order to expand the functionality by forming nested pulse sequences, a second register and a P-trigger are introduced into it, D-input of which is connected to the input bus and connected to the zero-pulse input of the pulse counter, the output is connected to the zero-input of the second register, and the input is connected to the control input of the selector-multiplexer with data input of the first register and with the output of the counter, the input of which is connected via a delay element to the clock bus and to the clock inputs of the first and second registers, the first output of the first of which is connected to the first input of the first group of inputs and the last input of the second group of inputs of the selector-multiplexer, the second output of the first register is connected to the second input of the first group of inputs and the penultimate input of the second group of inputs of the selector-multiplexor, the last output of the first register is connected to the last input rvoy group of inputs and the first input of the second group selektoramultipleksora inputs selektoramultipleksora outputs coupled to data inputs of the second register, whose outputs are connected to respective output lines. | Compiled By, Chizhikov