SU1182653A1 - Pulse frequency multiplier - Google Patents

Abstract

A MULTIPLACE OF PULSES FREQUENCY, containing a reference frequency generator, the output of which is connected to the first input of the first element I, the second input of which is connected to the trigger output, the output to the counting input of the first pulse counter, the code inputs of which are connected to the corresponding outputs of the code register of the whole part of the multiplication factor, the output is with the input of the delay element and with the first input of the trigger, the second pulse counter, the second element AND, the input and output bus, characterized in that, in order to expand the functional Possibilities by providing the possibility of multiplying the frequency of the pulses by a fractional coefficient and increasing the reliability, the first and the second bus sets the multiplication factor code, the first and second elements OR, the fractional part code register and the decoder zero, the code inputs of which are connected to the corresponding register outputs the code of the integer part of the multiplication factor, the first output is connected to the second input of the trigger, the second output is the first input of the second element And, the second input of which is connected to i a trigger input with a recording input of the first pulse counter and a trunk with an input bus, an output with the first input of the first OR element, the second C input of which is connected to the output of the delay element, the output with a counting input of the second pulse counter, the code inputs of which are connected by t corresponding outputs the code register of the fractional part of the multiplication factor, the output to the first input of the second element OR, the second input of which is connected to the output of the first element AND, the output to the output bus, while the code inputs of the code register of the whole clock The coefficients of the multiplication factor and the register of the fractional part code of the multiplication factor are connected respectively to the first and second buses of the installation of the multiplication factor code.

Description

one

The invention relates to a pulse technique and can be used in frequency-pulse computing and measuring devices.

The purpose of the invention is to enhance the functionality by allowing the frequency of the pulses to be multiplied by a fractional factor and increasing reliability. I. .

The drawing shows the electrical circuit of the device.

The pulse frequency multiplier contains a generator 1 of the reference frequency, the output of which is connected to the first input of the first element 2, the second input of which is connected to the output of the trigger 3, the output to the counting input of the first counter of 4 pulses, the code inputs of which are connected to the corresponding output of the register 5 of the whole code parts of the multiplication factor, the output is with the input of the delay element 6 and with the first input of the trigger 3, the second pulse counter 7, the second element 8 I, the input and output buses 9 and 10, the first and second buses 11 and 12 of setting the code: efficiency The multiplication unit, the first and second elements 13 and 14 OR, the register 15 of the fractional part code of the multiplication factor and the decoder 16 zero, the code inputs of which are connected to the corresponding outputs of the register 5 code of the integer part of the multiplication factor, the first output is connected to the second input of the trigger 3, the second output - with the first input of the second element 8 And, the second input of which is connected to the third input of the trigger 3, to the recording input of the first counter 4 pulses and to the input bus 9, the output - to the first input of the first element 13 OR, the second input of which is connected to the output of the delay element 6, the output with the counting input of the second counter 7 pulses, the code inputs of which are connected to the corresponding outputs of the register 15 to the fractional part of the multiplication factor, the output to the first input of the second element 14 OR, whose second input is connected to the output of the first element 2 And, the output is from the output bus. 10, while the code inputs of the register 5 of the code of the integer part of the multiplication factor and register 15 of the code of the fractional part of the multiplication factor are connected respectively to per 6532

howling and second tires 11 and 12 set the multiplication factor code.

The register 5 of the code for the integer part of the multiplication factor a and the first counter of 4 pulses is a binary divider, 17 frequencies, and the second counter of 7 pulses and register 15 of the fractional part code of the multiplication factor are a binary multiplier 18

the frequencies, the inputs of the record (not shown) of registers 5 and 15 are used to enter in them the new values of the multiplication factor code.

The device works as follows.

in a way.

In the initial state, the registers 5 and 15 contain codes of the whole and fractional parts of the multiplication factor, respectively; trigger 3 is in

zero state.

If the code on bus 11 is zero, then the zero state of register 5 is allocated using the decoder 16. The signal generated last at the first output blocks trigger 3 in the zero state, and the output signal from the second output of the decoder 16 allows the input pulses from bus 9 to pass through elements 8 and

and 13 OR, the multiplier 18 and the element 14 OR on the bus 10. Thus, the input frequency pulses are multiplied by the code received on the bus 12.

If the code of the integer part of the multiplication factor arriving at bus 11 is not equal to zero, the signals from the outputs of the decoder 16 close element 8 And enable the operation of trigger 3. The input pulse from bus 9 writes to counter 4, which is made subtractive (counter 4 is made and summing, but in this case it is necessary from the register 5

Dimo write additional code), code from register 5 and switches trigger 3 to one state. In this case, the pulses from the output of the generator 1 through the element 2 and pass

on the counting input of the counter 4 and then through the element 14 OR on the bus 10. After filling the counter 4, a pulse appears at its output, which switches the trigger 3 to zero

condition. Thus, an output frequency is generated that is proportional to. The code on bus 11 and the pulse frequency of the generator 1 is national. Simultaneously; 31 but the output pulse of counter 4 through the elements .6 and 13 goes to the counting input of counter 7 and then through element 4 OR to bus 10. Since the frequency of the output pulses of counter 4 is equal to the frequency of the input pulses on bus 9, it is thus on the bus 10 a pulse sequence appears, the average pulse frequency of which. equal to the sum of 182 -10 53. -4 Research institutes of the frequency of the input pulses, the frequency of the pulses of the generator 1 and the code on the bus 11, as well as the frequency of the input pulses and the code on the bus 12. The delay element 6 serves to time the input pulses of the element 14 OR, and in many cases, the input. it is not required in devices. ;

nineteen

Hd

Yes

Claims (1)

A PULSE FREQUENCY MULTIPLIER, comprising a reference frequency generator, the output of which is connected to the first input of the first AND element, the second input of which is connected to the trigger output, the output - with the counting input of the first pulse counter, the code inputs of which are connected to the corresponding outputs of the code register of the integer part of the multiplication coefficient, output - with the input of the delay element and with the first input of the trigger, the second pulse counter, the second element And, the input and output buses, characterized in that, in order to expand the functionality by providing the possibility of multiplying the pulse frequency by a fractional coefficient and improving reliability, the first and second buses for setting the multiplication coefficient code, the first and second OR elements, the code register of the fractional part of the multiplication coefficient and a zero decoder, the code inputs of which are connected to the corresponding outputs, are introduced into it the code register of the integer part of the multiplication coefficient, the first output is connected to the second input of the trigger, the second output is to the first input of the second AND element, the second input of which is connected to the third input trigger, with the recording input of the first pulse counter and with the input bus, the output - with the first input of the first OR element, the second · input of which is connected to the output of the delay element, the output - with the counting input of the second pulse counter, the code inputs of which are connected by t the corresponding outputs of the code register fractional part of the multiplication factor, the output is with the first input of the second OR element, the second input of which is connected to the output of the first AND element, the output is with the output bus, while the code inputs of the code register of the integer part of the coefficient are multiplied The code register and register of the fractional part of the multiplication coefficient are connected respectively to the first and second buses for setting the multiplication coefficient code. 1 182653 '