SU1555839A1 - Pulse repetition frequency multiplier - Google Patents

Abstract

The invention can be used in automatic control systems for processing low frequency signals, as well as in digital measuring equipment of infra-low frequencies. The purpose of the invention is to increase the speed by doubling the frequency of updating the input information - achieved by introducing an additional counter 6 pulses and organizing new functional connections. The device also contains a pulse shaper 1, a storage register 2, delay elements 3, 5, a pulse counter 4, a frequency divider 7, a clock pulse generator 8, a frequency divider 9 with a variable division factor, an input 11 and an output 10 bus. 1 il.

Description

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The invention relates to computing and measuring technology and can be used in automatic control systems for processing low frequency signals, as well as in digital measuring equipment at low frequencies.

The purpose of the invention is to increase the speed by doubling the frequency of updating the output information.

The drawing shows an electrical multiplication circuit of a pulse frequency multiplier.

The device contains a pulse former 1, the output of which is connected to the installation input of the storage register 2 and to the input of the first delay element 3, the output of which is connected to the installation input of the counter C pulses and through the second delay element 5 to the installation inputs of the additional counter 6 pulses and divider 7 frequency, the clock input of which is connected to the output of the generator of 8 clock pulses and with the clock input of the frequency divider 9 with a variable division factor, the output of which is connected to the output bus 10, information The input inputs are connected via the storage register 2 to the outputs of the pulse counter k, the information inputs of which are connected to the outputs of the additional pulse counter 6, the counting input of which is connected to the counting input of the pulse counter 4 and to the output of the frequency divider 7, the input of the pulse former 1 is connected to the inlet bus 11.

The pulse frequency multiplier operates as follows.

Bus 11 receives square-wave input frequency pulses, the duty cycle of which is not necessarily equal to two.

On the front and the edge of these pulses, the shaper 1 generates short pulses, which enter into the register 2 the code present at the outputs v of the counter k. The same short pulses, passed through element 3, are entered into counter 1, the code present at the outputs of counter 6, and, after passing further through element 5, the counter 6 and the divider 7 are reset to the initial state (the last one is set to decrease the quantization error -

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K + 0.5, where K is the device multiplication factor).

After this, counter 6 starts counting the pulses again from the output of divider 7, and the counter, counting the same pulses, adds to the code previously entered into it from counter 6 a number corresponding to the current value of the period portion of the input pulses on the bus 11.

Thus, by the time each pulse appears at the output of shaper 1, in counter 6 there is a value of a part of the period of input pulses on bus 11, and the counter is the value of the whole period of input pulses entering the register 2.

In accordance with this code value, output frequency pulses are generated on bus 10 by divider 9.

Claims (1)

Invention Formula five 0 five A pulse frequency multiplier comprising a clock pulse generator, the output of which is connected to the clock inputs of a frequency divider and a frequency divider with a variable division factor, the output of which is connected to the output bus, the information inputs are connected to the outputs of the storage register, the information inputs of which are connected to the outputs of the pulse counter, the counting input of which is connected to the output of the frequency divider, the setup input - with the output of the first delay element, the input of which is connected to the setup input A register of the storage and, through a pulse driver, with an input bus, and a second delay element, characterized in that, in order to increase speed by doubling the update rate of the output information, an additional pulse counter, the outputs of which are connected to the information inputs of the pulse counter, is introduced into it. , the counting input - with the output of the frequency divider, the installation input of which is connected to the installation input of the additional pulse counter and through the second delay element - to the installation input of the pulse counter all 0 0