SU1411946A1 - Device for selecting the last pulse in a series - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital information processing devices. The invention improves the accuracy of the formation of the last pulse of the series with an unstable pulse period. To achieve this goal, the second register 11, the decoder 9, the adder 10, the pulse shaper 12, the element OR 6, the two flip-flops 1 and 2, the second element 4, the control bus are added to the device. The device also contains the first element I 3, a pulse counter 5, subtracting the pulse counter 7, shifting the register 8, buses 13-16. When the device operates, a code is formed at the outputs of the adder 10 ,. equal to the code measured by the counter 5 of the time interval between the first and second pulse of the stack and the tolerance code for instability. The operation of the device is explained in the time diagrams provided in the description of the invention. 2 Il. / L

Description

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The invention relates to a pulse technique and can be used in digital information processing devices.

The purpose of the invention is to increase the accuracy of the formation of the last pulse of the series with an unstable period of the pulse following,

I FIG. 1 shows the electrical circuit of the device;

I in FIG. 2 are timing diagrams, which show his work,

i Device for the last

first pulse in the series contains the first 1 and second 2 triggers, the first 3 and second 4 elements AND, the counter 5 pulses, the element OR 6, subtracting the counter 7 pulses, shifting the register 8, the decoder 9, the adder 10, the register 11, the driver 12 pulses, the input bus 13, the clock bus 14, the information bus 15, the output bus 16, the input bus 13 connected to the information input of the shift register 8, the synchronization input of which is connected to the bus 14 clock pulses, and the first input - with the corresponding1 (these inputs are the decoder a 9, the first output of which is connected to the recording input of the readout counter 7, the second output to the first input of the element OR 6, the third output - to the R input of the pulse counter 5, and the fourth output to the S input trigger. If the R input connected to the output of the Lm 6, and the output to the second 11th inlet of the element 4 and the C input of the trigger 1, the R input of which is connected to the second input of the element OR 6 and the output; (ohm of the driver 12 pulses and 1 || output - with the first input of the element FROM WHITE, which is connected to the output canine 16 and the input of the driver 12 Impulses, the second input - with the output ; And 4, counting counter input - pulses and counting input, subtract njero counter 7 pulses, and the third E | HOD - with the output of the subtracting counter | 7 pulses, information inputs 1 (| are connected to the corresponding (and the outputs of the adder, the first group B1 of which is connected with the corresponding outputs of the counter 5 impulses cpv, and the second group of inputs - with the corresponding 1 outputs of the register 11, in {which moves are connected to the corresponding information buses 15,

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five

0

five

0

five

0

five

0

five

which are used to set the tolerance code for changing the follow-up period of the input pulses.

The frequency of the clock pulses is selected from the condition of ensuring the specified accuracy of measuring the pulse period. Higher frequency provides greater accuracy. The number of bits of counter 5 should provide for counting the number of pulses of the clock frequency over the time between pulses of a series. The adder 10 must provide the addition of the code at the output of the counter 5 with the code at the output of the register 11, the width of the subtractive counter 7 must provide the recording of the result of the addition from the output of the adder 10, the shift register 8 must have at least four bits and the decoder 9 must have at least four inputs and outputs. The pulse duration at the output of the imaging unit 12 should be sufficient to reset the flip-flops 1 and 2,

A device for separating the last pulse in the series operates as follows.

Before starting, triggers 1 and 2 are reset. In this case, the outputs of the triggers 1 and 2 have a low potential, the elements And 3 and 4 are closed by the first inputs. The clock frequency from the bus 14 to the output bus 16 does not pass, i When a series of pulses arrive on the bus 13, the shift register 8 records a signal that advances along the shift register 8 in pulses of the clock frequency. Depending on the potential at the outputs of the shift register 8 (Fig , 2c, d, e, f) decoder 9 generates pulses at its outputs (figs, 2g, and, k, l). Thus, at the outputs of the decoder 9 four pulses are shifted relative to each other, tied in time to the leading edge of the pulse series. The pulse from the first output of the decoder 9 (fig, 2g) through the element OR 6 enters the R-input of the trigger 2 and confirms its initial state (fig, 2m). The impulse from the second output of the decoder 9 (fig, 2i) enters the pre-entry subtractive counter 7 and writes the code into it, the presence at its inputs of the preset, Emyuls from the third output is decrypted

pa 9 (fig. 2k) arrives at the R input of counter 5 and sets it to the zero state (fig. 2p). The impulse from the fourth output of the decoder 9 (Fig. 2L) arrives at the S input of trigger 2 and sets it into the unit state, in which its output has a high potential (Fig 2m). From this time, the AND 4 element is open at the first input and the clock pulses from the bus 14 begin to flow through it to the input of counter 5, to the input of the deducting counter 7 and to the input of the element 3. As the trigger 1 changes its state along the trailing edge of the input pulse, then at the considered time the element AND 3 is closed at the first entrance, and at the output of the device Twa pulses are absent.

Upon arrival on bus 13 of the second pulse, pulses are formed at the outputs of the decoder 9 (Fig. 2g, and, k, l No. pulse from the first output of the decoder 9 through the element OR 6 sets trigger 2 to the initial state, while trigger 1 switches Element 4 is closed. Pulses no longer arrive at the input of counter 5. A code proportional to the pulse following period is stored in counter 5. At the outputs of adder 10, there is a code equal to the code of the measured counter 5 of the time interval between the first and second bursts of the packet and the unstabilized tolerance code ness

Claims (1)

Claims An apparatus for isolating a last pulse in a series comprising a tire. clock pulses, input bus connected to the first input of the first register, first counter, counting input ten IS 20 ). 25 4119464 which is connected to the counting input of the second counter, the output of which is co30 35 . 40 counter, Dinen with the first input of the first element I, the output of which is connected to the output bus, is different so that in order to increase the accuracy of the formation of the last pulse of the series with an unstable pulse following period, a second register, a decoder, an adder, a pulse shaper are entered into it , the OR element, two triggers, the second AND element, control buses connected to the corresponding inputs of the second register, the outputs of which are connected respectively to the first group of inputs of the adder, the second group of inputs of which are connected to Corresponding to the first outputs of the first pulse counter, and the outputs to the corresponding information inputs of the SECOND pulse pulse, whose recording input is connected to the first output of the decoder, and the counting input to the output of the second And element, and the second input of the first And element, the third input to the first output trigger, and the output through the pulse shaper with the first input of the OR element and the first input of the first trigger, the second input of which is connected to the output of the second trigger and the first input of the second element, And the second input which is connected to the clock pulse bus and the second input of the first register, the outputs of which are connected to the corresponding inputs of the decoder, the second output of which is connected to the second input of the OR element, the third output - to the installation input of the first counter, and the fourth output - to the first input of the second trigger, the second the input of which is connected to the output of the element OR. N P Yayay ---- ДДШ1А1Ш 1ШЙДДЯЯАя y ////////////////////////////////////// RU Editor N, Bobkova Compiled by Ermakov Tehred M. Didyk Proofreader c. Girn to Order 3671/54 Circulation 928 VNIIPI USSR State Committee for inventions and discoveries I3035, Moscow, Zh-35, Raushsk nab., 4/5 Subscription