SU1357914A1 - Device for measuring time intervals - Google Patents

Abstract

The invention relates to a pulse technique and can be used to measure a series of time intervals. The purpose of the invention, the enhancement of functionality, is achieved by eliminating the differential nonlinearity of the transformation. To do this, a device containing a reference generator 1, a key 2, a pulse counter 3, which can be executed with parallel transfer, input bus 5 Start, input buses 9 and input bus 10 Reset, an RS-trigger 4 is additionally entered, n buffer stages 6 , n delay blocks 7 and n synchronization blocks 8. The use of blocks 7 and 8 makes it possible to read the current state of a continuously operating counter 3 with a parallel transfer to a quasi-static state. At the end of the measurement cycle, the counter 3 switches the RS flip-flop 4 to the zero state. After the arrival of the control signals on the bus 10, the measurement cycle is repeated. 2 Il. C /) ate -j with

Description

The invention relates to a pulse technique and can be used to measure a series of time intervals.

The aim of the invention is to enhance the functionality by eliminating the differential non-linearity of the transform.

Fig. 1 is a functional diagram of a device for measuring time intervals; 2 shows timing diagrams for the operation of the device.

The device contains a reference generator 1, a key 2, a pulse counter 3 (can be executed with parallel transfer), an RS flip-flop 4, an input bus 5 Start, n buffer stages 6, n blocks, delay, n blocks 8: synchronization, input buses 9 , input bus 10 reset.

The output of the reference generator 1 is connected to the input of the key 2, the control input of which is connected to a single: output of the RS flip-flop 4, the S-input of which is connected to the input bus 5, you-: the turn of the key 2 is connected to the combined first inputs n blocks 8 synchronization and with the counter input of the counter 3 bit outputs of which are connected to the information inputs of each of the n buffer stages 6, the control; the inputs of each of the n buffer stages 6 through the corresponding delay unit 7 are connected to the output of the corresponding unit 8, the second input of each of which It is connected with the corresponding input bus 9, the bus 10 Reset is connected to the control input of the counter 3, the overflow output of which is connected to the R input of the par 4.

The device works as follows.

By a signal arriving at the bus 10 Reset, the counter 3 is reset. The input pulse on bus 5 Start switches the RS-flip-flop 4 (Fig. 2a) to one state, which opens key 2, and the pulses of the reference generator 1 begin to flow to the counting input of counter 3 (Fig. 2b). The signals (i-1,2, ..., p) of the studied pulse sequences (Fig. 2c, d, g) are received via the corresponding input buses 9 to the second inputs, respectively

five

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synchronization blocks 8, in which the input signals of the studied pulse sequences are tied to a specific phase of the signals of the reference generator 1 that have passed through key 2. The output pulses of the synchronization blocks 8 delayed in the delay 7 blocks at the time of switching transients of counter 3 (Fig. 2i) ), arrive at the control inputs of the corresponding buffer stages 6 (FIGS. 2d, f, 3) by writing the current counter code 3 to the buffer stages 6. The use of synchronization blocks 8 and delay 7 allows Read the current state of a continuously operating binary counter 3 with a parallel transfer to a quasi-static state.

At the end of the measurement cycle, the overflow signal of the counter 3, which determines the end of the measurement cycle, switches the RS flip-flop 4 to the zero state. After the control signals come on bus 10 Reset, bus 5 starts the measurement cycle.

Claims (1)

Invention Formula A device for measuring time intervals, containing a reference generator, the output of which is connected to the key input, and a pulse counter, characterized in that, in order to expand its functionality, RS-flip-flop, n buffer stages, n synchronization blocks and n blocks are entered into it delays, the first inputs of the synchronization units are combined together and connected to the counting input of the pulse counter and the output of the key, the control input of which is connected to the single output RS of the trigger, the 8 input of which is connected to the Start bus, the R input of the trigger a is connected to the pulse counter overflow output, the bit outputs of which are connected to information inputs of n buffer stages, the control input of each of the n buffer stages through a corresponding delay unit is connected to the corresponding output of each of the n synchronization blocks, the second inputs of which are connected to the corresponding input buses, bus Reset is connected to the control input of the pulse counter.