SU1571610A1 - Device for orthogonal walsh-hadamard transform - Google Patents

Abstract

The invention relates to automation and computing and can be used in the technique of digital signal processing. The purpose of the invention is to increase speed. This goal is achieved due to the fact that the device includes two blocks of shift registers 1, 2, two registers 3, 4, switch 5, adder-subtractor 6, synchronization unit 7 and the corresponding communications between the nodes of the device. 4 il.

Description

FI.1

3157

The invention relates to automation and computing and can be used in digital signal processing techniques, such as compressing data, filtering signals, extracting features for pattern recognition, etc.

The purpose of the invention is to improve the speed of the device.

FIG. 1 is a functional diagram of the Walsh-Hadamard orthogonal transformation device; Fig.2 is a functional diagram of the synchronization unit; in fig. 3 - timing diagram of the synchronization unit; in fig. 4 is a Walsh-Hadamard graph-scheme conversion at.

The device contains the first block 1 of the shift registers, the second block 2 of the shift registers, the first register 3, the second register 4, the switch 5, the adder-subtractor 6, the synchronization block 7 and the device start input 8.

The synchronization unit (FIG. 2) contains a start input 8, a one-shot 10, delay elements 11.12, a clock pulse generator 13, a trigger 14, frequency dividers 15.16, a short pulse driver 17, OR elements 18-20 and outputs 21-25. .

The synchronization unit generates the necessary clock sequence as follows. A short sync pulse arriving at input 9 triggers a one-shot 10, which generates a strobe pulse to enable data to be written to blocks 1.2 of the shift registers. Delayed sync pulses from the outputs of elements 11,12 delays are used to record the original data and are combined in the corresponding elements OR 19.20 with clock pulses from the generator output 13 clock pulses. The start of the clock generator 13 is effected by a pulse from the output of the delay element 12. Clock pulses from the output of the generator 13 are fed to the input of the trigger 14 with a counting input, which generates a control pulse applied to the output of the synchronization unit 25. The pulses from the output of the counting trigger 14 are fed to the input of the first frequency divider 15, which divides

rNo.-n pulse frequency per o

N i at its output everyone has (+

0

five

6104

2) -and the pulse of the input sequence. The second frequency divider 16 divides the frequency of the input signal by n,

whereupon the output of this del-ed

tel will be n (r + 2) th pulse from the output

trigger 14. By the back edge of this pulse, the short pulse shaper 17 generates a pulse, which stops the generator 13. Thus, the generator 13 will form a clock sequence of n (N + 4) pulses.

At the beginning of each conversion cycle, the counting trigger 14, the frequency dividers 15.16 are reset to the initial state by applying a pulse from the output of the delay element 11 to their control inputs.

As resolution pulses for recording intermediate results of conversion from the first shift register unit 1 to the second shift register register unit 2, pulses from the outputs of the frequency divider 15 are used, which are combined with the output pulse of the one-oscillator 10 at the OR 18 element.

FIG. 3 shows the diagrams of the operation of the synchronization unit 7.

Diagrams 1 and 2 show, respectively, a sync pulse arriving at the device start input, a pulse from the output of delay element 12.

0

five

0

I

Diagrams 4-7 show the signals from the outputs of the generator 13, the trigger 14, the frequency divider 15, the frequency divider 16 and the short pulse shaper 17, respectively.

Diagram 3 shows a gating pulse from the one-shot output of a 10. According to the algorithm used, the following data conversion is performed on the input data sample represented by the column vector f of dimension N:

F-HN-f, (1)

where F is a column vector of Walsh-Hadamard coefficients;

HN - Walsh-Hadamard matrix of dimension NxN; N 2

where n is a positive integer.

five

The Walsh-Hadamard transforms are performed iteratively over n iterations using the formula:

, „“)

F (s

W HN

I

... (5 „.Н (5, -НИИ) f), (2)

515

where . .H (Nn) matrix size

NxN;

S., is a monomial permutation matrix.

L j

HN 1 n / g®, n, where 1 fj / i is the identity matrix on the order of N / 2; H1 is the Hadamard matrix of order 2;

.

Thus, the computational procedure (2) is implemented in n iterations, and each i-iteration reduces to multiplying the column vector of the results f by the matrix H (w1, which reduces to adding or subtracting the corresponding elements of the intermediate vector f, -., And reordering the elements of the result vector f; multiplying by a monomial matrix S. The essence of the permutation consists in dividing the array of elements of the vector f into arrays of even and odd elements and forming a rearranged vector ff by successively . Assumption these arrays, wherein the array of the odd elements of the vector f disposed in the first half of the resulting array can .perestanovki Rule defined by the following relation:

f.

f

 fj (2 (J-O + O, with j 1, N / 2, f, (2 - (j-), with j N / 2 + 1, N

The elements of the matrix S N are determined by the formula:

1, (i-1), at. N / 2.

N / 2

S (1, (i- f), with, N,

Oh, otherwise.

The device operates as follows.

The device is designed for a natural order of input data. However, when overwriting data from the first block 1 of the shift registers to the second block 2 of the shift registers, the device reorders the data according to rule (3), which requires reordering of the original data when writing to the first block 1 of the shift registers. It is necessary to finish them again

0

five

0

so that after rewriting into the second block of the 2 shift registers they appear in the natural order, i.e. before starting the calculations, the N signal samples are located at consecutive addresses, N in block 2 of the shift registers.

After the arrival of the sync pulse to the control input 8 of the device, the strobe pulses from the outputs of the synchronization block 7 are received at the recording resolution enable inputs of the first and second blocks 1.2.

The first clock pulse arriving at the input of block 1 of the shift registers from the output of block 7 of synchronization will produce a parallel recording of the initial

data to block shift registers 1.

Due to the fact that i input (, N) of the group (parallel input of information) of block 1 of shift registers is connected to the j-th information input of the device

1 - (j-0-I, j 1, N / 2,

-US NN N M 2

thirty

35

40

45

50

where Q,

the source data will be written to the shift registers of block 1 in a reordered form. The first clock pulse from the output of synchronization unit 7 will overwrite the reordered source data in unit 2 of shift registers, in which they will appear in registers with sequence numbers, N in natural order due to the corresponding connection of outputs of unit 2 of shift registers and inputs of unit 2 shift registers. After that, the device is ready to begin computing the orthogonal transform of the sample of source data of dimension N.

During the first N cycles of the first iteration, the N samples of the signal are shifted to the output of the 0th shift register of block 2, received at the input of register 3 and the first information input of switch 5. The switch operation can be described by the following rule:

 that

 2-1

then

-logical state at the control input of the switch;

-connection of the M-th information input of the switch

to the L-th exit;

M 1.3, 2-.

The first f (and the second f2 count (and then every odd and even count)) during two clock cycles due to delays on the registers 3,4 will simultaneously arrive at the information inputs of the adder-subtractor, the mode of which on the control input changes with each clock cycle. The f, + + ft in the third cycle of the first iteration is converted and the subsequent amounts in odd cycles of the first iteration are recorded in the shift register unit 1 under the action of the clock pulses at its input. The difference in the fourth cycle of the first conversion iteration (and the subsequent The stems in even iteration cycles will be recorded in shift register block 1. Thus, to the beginning (N + 4) of the first conversion iteration cycle on odd registers

   kN

shear block 1 will be recorded sums,

N and on odd shift registers - g

differences.

Such an operation corresponds to a conversion schedule (Fig. 4). In the (N + 4) -M cycle of the first iteration of the conversion to the recording resolution input, the input of the shift register 2 unit is supplied with a strobe pulse from the output of the synchronization unit 7, as a result of which (N + 4) -M clock pulse at the input of the shift register unit 2 will be overwritten in block 2.

On the second and subsequent iterations, the device operates in the same way.

At the end of the nth iteration, the transform coefficients fj,, N are written at sequential addresses in block 2 of the shift registers and will be stored there until the next conversion cycle.

Claims (1)

Invention Formula An orthogonal Walsh-Hadamard transform device containing the first and second blocks of N + 1 0 0 five 0 five 0 45 0 (where N is the conversion size) of the shift registers, the first register, the summator-subtractor and the synchronization block whose start input is the device start input, the first and second outputs of the synchronization block are connected respectively to the clock input and the shift enable input of the first block of shift registers the shift enable input of the second block of shift registers is connected to the third output of the synchronization block, the fourth output of which is connected to the clock inputs of the second block of shift registers and the first register, and the fifth output block Synchronization is connected to the control input of the adder-subtractor, characterized in that in order to improve performance, it introduced a second register and a switch, wherein the data input of the 1st (, N) of the shift register n the first- shift register unit is a j-m (for i - even, j (N + i) / 2 when i - odd) information input device, and the output of the 1st shift register of the first block of shift registers is connected to the information input of the j-ro shift register of the second block of shift registers, the output of the first shift register of which is connected to the first information input of the switch and the information input of the first register The output of which is connected to the second information input of the switch and the information input of the second register, the output of which is connected to the third information input of the switch, the first and second output Which are connected respectively to the first and second information inputs of the adder-subtractor, the output of which is connected to the information input (N + 1) -ro of the shift register of the first block of shift registers, the fourth and fifth outputs of the synchronization unit are connected respectively to the clock input of the second register and control switch input. FIG. 2 tfteJ A + 8