SU788363A1 - Digital frequency multiplier - Google Patents

Description

one

The invention relates to measuring and computing techniques and can be used in devices for various purposes, in particular in devices for monitoring the state of mechanical systems with rotating parts using electronic methods for analyzing and measuring the frequency components of vibrations.

A device is known to multiply 10 the frequency of a periodic pulse, containing a reference frequency divider with a division factor equal to the coefficient, multiplication K, a reference frequency pulse counter, a counter to 5 pulses, drivers, memorization registers, two transfer units and a control unit Ij

However, this device is characterized by a discreteness error, 20 due to the non-multiplicity of the number N of the pulses of the reference frequency generator f ,, .., received 1Х during the period T of the input frequency fx and the division factor K. As a result, by the end of each period TX in the divider, a number may remain, representing the fractional part of the quotient N / K, which is expressed in the error period of the output AOR pulses

sequences in the range reaching T (5tl

A periodic pulse frequency multiplier is also known, containing a reference frequency divider with a division factor equal to the multiplication factor, a pulse counter, a reference frequency pulse counter, drivers, a memory register, two transfer units and a control unit, an additional register is stored in it, a decoder , coincidence elements, delay lines and an OR element, and the outputs of the frequency divider are connected to an additional memory register, the outputs of which are connected to i ladies decoder. The outputs of the decoder are connected to the first inputs of the coincidence elements, the second inputs of which are combined and connected to the output of the output driver, the output of the first directly, and the outputs of the rest through delay lines connected to the inputs of the OR element. In the device, to reduce the error, the sequence of pulses from the output of the output driver is passed through a line with a delay t determined by the state of the additional register by the decoder 2. The purpose of the invention is to improve the accuracy of frequency multiplication. The goal is achieved by sequentially including an angry pulse counter, a first memory register, a transfer unit and a reference frequency pulse counter in the frequency multiplier, containing a reference frequency divider, and the control input of the transfer unit is connected to the output counter of the reference frequency pulse counter, and I remember one register, the inputs of which are connected to the outputs of the reference frequency divider, the control unit, to the input of which the input signal is fed, the first output is connected to the installation inputs of the reference frequency divider and pulse generator, a second output with register entry inputs, an OR element, delay lines, a match element and a decoder whose outputs are connected to the first inputs of the match element, the second inputs of which are combined and connected to the output of the reference frequency pulse counter, the output of the first match element directly , and the outputs of the rest through the delay lines are connected to the inputs of the OR element, a prohibition element is entered, the output of which is connected to the counting input of the counter of the reference frequency pulses, and the modulo This multiply, the inputs of which are connected to the outputs of the second memory register, the clock input to the output of the OR element, the output to the inputs of the decoder, and the overflow output to the first input of the propelling element, the second input of which has a reference signal. The drawing shows a structural electrical circuit of a digital frequency multiplier. The device contains a divider 1 reference frequency with a division factor K, a counter 2 pulses formed during division, the first memory register 3, transfer unit 4, counter 5 frequency reference pulses, the second memory register 6, control block 7, element OR 8, a decoder 9, elements 10 of a match, delay lines 11, an adder 12 modulo a multiplication factor -K, and a prohibition element 13. The first output of control unit 7 is connected to the setup inputs of the divider 1 of the reference frequency and the counter of 2 pulses, the second - to the inputs of the zag.psi registers 3 and 6. The input of the control unit 7 has an input signal and the input of the divider 1 is the reference signal Information outputs the divider 1 is connected (from the inputs of the register 6, whose outputs are connected to the inputs of the adder 12, the clock input of which is connected to the output of the element OR 8, the overflow output to the first input of the prohibition element 13, to the second input of which the reference signal is fed, the output of the sum to inputs to the decoder 9. The information outputs of the counter 2 pulses are connected to the inputs of the register 3, the outputs of which are connected to the counter of the reference frequency pulses through the transfer unit 4. The clock input of the counter 5 pulses is connected to the output of the inhibit element 13, to the control input of the transfer unit 4 and to the combined the inputs of the match element 10, the first inputs of which are connected to the outputs of the decoder 9. The outputs of the match elements 10 (the first one directly, and the rest through the delay lines 11) are connected to the inputs of the element OR 8. The device operates as follows time. Each pulse of the multiplied frequency fx is fed to the input of the control unit 7, in which an information recording pulse is generated in registers 3 and 6 and the pulse is set to the zero state of divider 1 and counter 2. The pulses from the output of divider 1, the frequency of which is equal to fgn / K, is fed to the input of counter 2. In one period T) (multiplied frequency f, the input of counter 2 receives the number of pulses equal to. In divider 1, the residual number m is formed at the end of the TX period, due to the non-multiplicity of the number N of reference frequency pulses received at the input Delhi tel 1 for the time T j, the division factor K (). After the next pulse of the multiplied frequency f arrives, the number Ny is written to register 3, and simultaneously (using the same signal) the number m from divider 1 is written to register 6 and fed to the input of accumulating adder 12. The reference frequency pulses are continuously fed through the prohibition element 13 to the input of the counter 5 reference frequency pulses, which operates in the subtraction mode and reduces the number recorded in it. As soon as the state of all the triggers of the counter becomes zero, a pulse appears at its output, which, arriving at the control input of transfer unit 4, transfers the number NK from register 3 to counter 5. As a result, the output of counter 5 forms a sequence of pulses with the period (in the case of ni 0). op - However, if, the period of the pulses at the output of the counter 5 is less than the required value and the value OadOk -: Odnde.p YTSy; - "s :: -; - m T - - T - T K to

From here

 , t-o. Thus, if we increase the period of the following pulses at the output of counter 5 by the value - T, then the discreteness error will be reduced. To do this, it is necessary to delay the first pulse from the output of counter 5 for the time Top, the second - the third - for etc. In this case, the period of the pulse at the output of the device will be

G „

in X

The period correction of the output pulse sequence is carried out as follows.

The first pulse from the output of the counter 5 is fed to the inputs of the coincidence elements 10. The decoder 9 analyzes the state of the adder 12, the outputs of the sum of which will be the number t, and gives the resolving potential to the input of the corresponding match element 10. The number of output tires of the decoder 9 is determined by how many times it is necessary to reduce the discreteness of the period at the output of the device, and can reach the value K. In this case, if the resolving potential appears at the first input of that coincidence element 10, which directly connected to the input of the element OR 8. When K / n m .2K / n, the resolving potential appears on the decoder bus 9, connected to the coincidence element 10, the output of which is connected to the element OR 8 via delay line 11 with delay time Toii / fi at 2 connection pr proceeds through a delay line 11 with a delay time 2 etc. Thus, the first pulse at the output of the device is due to a delay proportional to the value of the number m. When the clock input of accumulating adder 12 arrives at the clock input, this pulse adds the number m to the sum, and the number of tons appears at the outputs of the sum of the adder 12. The decoder state 9 changes The second pulse from the output of counter 5 also receives a delay proportional to 2 m, the third one proportional to 3 m, the fourth one receives 4 m, and so on. If at any stage of the device operation the number im, where i is the number of the next pulse, exceeds the number K, then an overflow pulse appears at the output of the overflow output, which means that the next pulse from the output of counter 5 must be delayed by an amount greater than than tol. Element 13 of the prohibition on overflow signal prohibits: „: 1W impulse of the sequence.

which is equivalent to the delay of the next pulse from the output of the counter 5 by the value Тd „. With the help of the decoder 9, the coincidence elements 10 and the personal delay 11, this pulse is additionally delayed by an amount proportional to the remainder of the number in the adder. The time position of the subsequent pulses is also corrected in the same way.

m + i, rri K

element. 13 prohibition again excludes one pulse from the sequence fc, at the input of the counter 5.

Thus, the pulse repetition period at the output of the element OR 8 will be determined, taking into account the maximum error, by the expression

T T

t °

 8 OUT 1

those. the maximum discreteness error is reduced.

Claims (2)

1. USSR author's certificate number 357668, cl. H 03 K 5/01, 1972. 2. USSR author's certificate number 544112, cl. H 03 K 5/01, 1977. / X